Debesh K. Das

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 12

Top Topics

Boolean Functions

Functional Properties

Prime Implicants

Multiple Valued

Top Venues

Publications

Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya, Debesh K. Das
Power-aware partitioning and test time reduction for 3D-SoC. Innov. Syst. Softw. Eng. 20 (3) (2024)
Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh K. Das, Bhargab B. Bhattacharya
Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. VLSID (2022)
Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya
Improved Upper Bound on Independent Domination Number for Hypercubes. CoRR (2022)
Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das, Bhargab B. Bhattacharya
Fast algorithms for test optimization of core based 3D SoC. Integr. 77 (2021)
Joyati Mondal, Arighna Deb, Debesh K. Das
An Efficient Design for Testability Approach of Reversible Logic Circuits. J. Circuits Syst. Comput. 30 (6) (2021)
Tanusree Kaibartta, G. P. Biswas, Debesh K. Das
Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing. ATS (2020)
Sayantani Roy, Arighna Deb, Debesh K. Das
Delay Efficient All Optical Carry Lookahead Adder. VDAT (2019)
Arighna Deb, Debesh K. Das
Detailed Fault Model for Physical Quantum Circuits. ATS (2019)
Arighna Deb, Debesh K. Das
An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata. Microprocess. Microsystems 53 (2017)
Sabyasachee Banerjee, Subhashis Majumder, Abhishek Varma, Debesh K. Das
A placement optimization technique for 3D IC. ISED (2017)
Debabani Chowdhury, Debesh K. Das, Bhargab B. Bhattacharya, Tsutomu Sasao
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults. ISMVL (2016)
Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM J. Emerg. Technol. Comput. Syst. 12 (4) (2016)
Tanusree Kaibartta, Debesh K. Das
Testing of 3D IC with minimum power using genetic algorithm. IDT (2015)
Joyati Mondal, Debesh K. Das, Bhargab B. Bhattacharya
Design-for-testability in reversible logic circuits based on bit-swapping. ATS (2015)
Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. ISMVL (2015)
Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das
Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. DDECS (2015)
Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das
Partitioning-based test time reduction for core-based 3DICs. VDAT (2015)
Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya
Synthesis of Symmetric Boolean Functions Using a Three-Stage Network. ISED (2014)
Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao
Inadmissible Class of Boolean Functions under Stuck-at Faults. ISMVL (2014)
Manjari Pradhan, Debesh K. Das, Chandan Giri, Hafizur Rahaman
Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning. EWDTS (2014)
Rupali Mitra, Debesh K. Das, Bhargab B. Bhattacharya
On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties. ISVLSI (2014)
Arighna Deb, Debesh K. Das, Susmita Sur-Kolay
Modular Design for Symmetric Functions Using Quantum Quaternary Logic. ISED (2013)
Joyati Mondal, Debesh K. Das, Dipak Kumar Kole, Hafizur Rahaman
A design for testability technique for quantum reversible circuits. EWDTS (2013)
Manjari Pradhan, Chandan Giri, Hafizur Rahaman, Debesh K. Das
Optimal stacking of SOCs in a 3D-SIC for post-bond testing. 3DIC (2013)
Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya
Reversible synthesis of symmetric boolean functions based on unate decomposition. ACM Great Lakes Symposium on VLSI (2013)
Debesh K. Das, Debabani Chowdhury, Bhargab B. Bhattacharya, Tsutomu Sasao
Inadmissible Class of Boolean Functions under Stuck-at Faults. CoRR (2013)
Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Derivation of test set for detecting multiple missing-gate faults in reversible circuits. Comput. Electr. Eng. 39 (2) (2013)
Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. RC (2013)
Papia Manna, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization. ISED (2012)
Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits. ISED (2011)
Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya
Fault diagnosis in reversible circuits under missing-gate fault model. Comput. Electr. Eng. 37 (4) (2011)
Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. ISED (2011)
Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. Asian Test Symposium (2010)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Testable design of AND-EXOR logic networks with universal test sets. Comput. Electr. Eng. 35 (5) (2009)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. IEEE Trans. Instrum. Meas. 57 (12) (2008)
Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya
Optimum Test Set for Bridging Fault Detection in Reversible Circuits. ATS (2007)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. J. Electron. Test. 22 (2) (2006)
Hafizur Rahaman, Debesh K. Das
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. ASP-DAC (2005)
Biplab K. Sikdar, Samir Roy, Debesh K. Das
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. J. Electron. Test. 21 (1) (2005)
Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das
Synthesis of Testable Finite State Machine Through Decomposition. Asian Test Symposium (2005)
Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das
Cellular Automata Based Test Structures with Logic Folding. VLSI Design (2005)
Hafizur Rahaman, Debesh K. Das
A Simple Delay Testable Synthesis of Symmetric Functions. AACC (2004)
Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian
Design & Test Education in Asia. IEEE Des. Test Comput. 21 (4) (2004)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. ASP-DAC (2004)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. VLSI Design (2004)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. Asian Test Symposium (2003)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. J. Comput. Sci. Technol. 17 (6) (2002)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
A New Synthesis of Symmetric Functions. VLSI Design (2002)
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. VLSI Design (2002)
Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. VLSI Design (2001)
Biplab K. Sikdar, Samir Roy, Debesh K. Das
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. Asian Test Symposium (2001)
Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
Cellular automata as a built in self test structure. ASP-DAC (2001)
Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya
Isomorph-Redundancy in Sequential Circuits. IEEE Trans. Computers 49 (9) (2000)
Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya
Synthesis of Symmetric Functions for Path-Delay Fault Testability. VLSI Design (1999)
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. ASP-DAC (1999)
Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. VLSI Design (1998)
Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya
Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. ASP-DAC (1998)
Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya
Isomorph-redundancy in sequential circuits. VTS (1996)
Debesh K. Das, Bhargab B. Bhattacharya
Testable design of non-scan sequential circuits using extra logic. Asian Test Symposium (1995)