Surajit Kumar Roy

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 22

Top Topics

Cost Effectiveness

Thermal Conductivity

Integrated Circuit

Fault Detection

Top Venues

J. Electron. Test.

Publications

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs. Integr. 94 (2024)
Tapobrata Dhar, Ranit Das, Chandan Giri, Surajit Kumar Roy
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection. J. Electron. Test. 39 (4) (2023)
Sourav Ghosh, Surajit Kumar Roy, Chandan Giri
Cost Effective Single Target Sample Preparation on Digital Microfluidic Biochip. iSES (2023)
Sourav Ghosh, Surajit Kumar Roy, Chandan Giri
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation. J. Electron. Test. 39 (1) (2023)
Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation. Microelectron. J. 128 (2022)
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs. ACM J. Emerg. Technol. Comput. Syst. 18 (4) (2022)
Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
Hardware Trojan Horse Detection through Improved Switching of Dormant Nets. ACM J. Emerg. Technol. Comput. Syst. 17 (3) (2021)
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Sourav Ghosh, Surajit Kumar Roy, Chandan Giri
Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets. J. Electron. Test. 37 (1) (2021)
Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs. ISDCS (2020)
Priyanka Naskar, Tapobrata Dhar, Surajit Kumar Roy
Hardware Trojan Detection Using Improved Testability Measures. ISDCS (2020)
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing. J. Electron. Test. 35 (5) (2019)
Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
Hardware Trojan Detection by Stimulating Transitions in Rare Nets. VLSI Design (2019)
Sourav Ghosh, Dolan Maity, Arijit Chowdhury, Surajit Kumar Roy, Chandan Giri
Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip. ATS (2019)
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
Identification of Faulty TSV with a Built-In Self-Test Mechanism. ATS (2018)
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Identification of Faulty TSVs in 3D IC During Pre-Bond Testing. VLSI Design (2018)
Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs. VDAT (2018)
Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
Modeling and Analysis of Transient Heat for 3D IC. VDAT (2017)
Sudeep Ghosh, Surajit Kumar Roy, Hafizur Rahaman, Chandan Giri
TSV repairing for 3D ICs using redundant TSV. ISED (2017)
Surajit Kumar Roy, Chandan Giri
Design-for-test and test time optimization for 3D SOCs. ITC (2017)
Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
Faulty TSVs Identification in 3D IC Using Pre-bond Testing. VDAT (2017)
Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
Optimization of Test Wrapper for TSV Based 3D SOCs. J. Electron. Test. 32 (5) (2016)
Surajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. VLSI-SoC (2015)
Surajit Kumar Roy, Kaustav Roy, Chandan Giri, Hafizur Rahaman
Recovery of faulty TSVs in 3D ICs. ISQED (2015)
Sumit Dhuwalia, Nikhil Khemka, Prince Gupta, Surajit Kumar Roy, Chandan Giri
Test Time Optimization for 3D-SICs Having Multiple Towers. iNIS (2015)
Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. IET Comput. Digit. Tech. 9 (5) (2015)
Surajit Kumar Roy, Payel Ghosh, Hafizur Rahaman, Chandan Giri
Session Based Core Test Scheduling for 3D SOCs. ISVLSI (2014)
Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri, Hafizur Rahaman
Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. 3DIC (2013)
Surajit Kumar Roy, Joy Sankar Sengupta, Chandan Giri, Hafizur Rahaman
Power constraints test scheduling of 3D stacked ICs. IDT (2013)
Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs. IDT (2013)
Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri
Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing. ISED (2012)
Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahman
Testing 3D stacked ICs for post-bond partial/complete stack. MWSCAS (2012)
Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahaman
Post-bond Stack Testing for 3D Stacked IC. VDAT (2012)
Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs. ISVLSI (2011)
Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman
Optimization of Test Wrapper for TSV Based 3D SOCs. ISED (2011)
Surajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman
Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. ISED (2011)