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Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips.
Surajit Kumar Roy
Chandan Giri
Hafizur Rahaman
Published in:
IET Comput. Digit. Tech. (2015)
Keyphrases
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integrated circuit
three dimensional
built in self test
software architecture
range images
real time
genetic algorithm
test cases
hardware description language
neural network
d objects
event driven
electron beam