Login / Signup
iNIS
2015
2017
2015
2017
Keyphrases
Publications
2017
Amit Singh Rajput
,
Manisha Pattanaik
,
R. K. Tiwari
Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology.
iNIS
(2017)
Sauvagya Ranjan Sahoo
,
Sudeendra Kumar K
,
Abhishek Mahapatra
,
Ayas Kanta Swain
,
Kamala Kanta Mahapatra
On-chip RO-Sensor for Recycled IC Detection.
iNIS
(2017)
Ashish Sharma
,
Yogendra Gupta
,
Sonal Yadav
,
Lava Bhargava
,
Manoj Singh Gaur
,
Vijay Laxmi
A Power, Thermal and Reliability-Aware Network-on-Chip.
iNIS
(2017)
Monalisa Das
,
Alak Majumder
,
Abir J. Mondal
,
Bidyut K. Bhattacharyya
A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application.
iNIS
(2017)
Abir J. Mondal
,
Alak Majumder
,
Bidyut K. Bhattacharyya
A Design Methodology for MOS Current Mode Logic VCO.
iNIS
(2017)
Anirban Sengupta
,
Deepak Kachave
,
Shubha Neema
,
Panugothu Sri Harsha
Reliability and Threat Analysis of NBTI Stress on DSP Cores.
iNIS
(2017)
Nagendra Babu Gunti
,
Karthikeyan Lingasubramanian
Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR.
iNIS
(2017)
Sudeendra Kumar K
,
Sauvagya Ranjan Sahoo
,
Abhishek Mahapatra
,
Ayas Kanta Swain
,
Kamala Kanta Mahapatra
Security Enhancements to System on Chip Devices for IoT Perception Layer.
iNIS
(2017)
Vipul Kumar Mishra
,
Anirban Sengupta
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis.
iNIS
(2017)
Saranyu Chattopadhyay
,
Kaustav Brahma
,
Arkaprova Ray
,
Mrigank Sharad
STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures.
iNIS
(2017)
Vipul Kumar Mishra
Cost Aware Majority Logic Synthesis for Emerging Technologies.
iNIS
(2017)
Deepak Soni
,
Dheeraj Sharma
,
Shivendra Yadav
,
Mohd. Aslam
,
Dharmendra Singh Yadav
,
Neeraj Sharma
Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor.
iNIS
(2017)
Gurveen Vaseer
,
Garima Ghai
,
Pushpinder Singh Patheja
A Novel Intrusion Detection Algorithm: An AODV Routing Protocol Case Study.
iNIS
(2017)
Himanshu Thapliyal
,
T. S. S. Varun
,
Edgard Muñoz-Coreas
,
Keith A. Britt
,
Travis S. Humble
Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth.
iNIS
(2017)
Rajani Suthar
,
Kirti S. Pande
,
N. S. Murty
Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique.
iNIS
(2017)
Subhendu Kumar Sahoo
,
Gangishetty Akhilesh
,
Rasmita Sahoo
Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET.
iNIS
(2017)
Bipasha Nath
,
Alak Majumder
Binary Counter Based Gated Clock Tree for Integrated CPU Chip.
iNIS
(2017)
Soudip Sinha Roy
Fault Tolerance and Temperature Stability: The Dynamic Error Estimation in Quantum-Dot Cellular Automata.
iNIS
(2017)
Pratima Chatterjee
,
Prasun Ghosal
Realizing All Logic Operations Using mRNA-Ribosome System as a Post Si Alternative.
iNIS
(2017)
Mohammed Ahmed
Digital Video Stabilization- Review with a Perspective of Real Time Implementation.
iNIS
(2017)
Soudip Sinha Roy
Towards the Approximation of Cell Wise Switching Time in Quantum-Dot Cellular Automata.
iNIS
(2017)
Syed Samsuz Zaman
,
Pankaj Kumar
,
Manash Pratim Sarma
,
Ashok Ray
,
Gaurav Trivedi
Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications.
iNIS
(2017)
Shivram Mansore
,
Radheshyam Gamad
,
D. K. Mishra
A Single-Ended Read Decoupled 9T SRAM Cell for Low Power Applications.
iNIS
(2017)
Nagendra Babu Gunti
,
Karthikeyan Lingasubramanian
Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme.
iNIS
(2017)
Alak Majumder
,
Pritam Bhattacharjee
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip.
iNIS
(2017)
Manoj R
,
Adrian Fernandez
Rapid Prototyping IoT End Applications Using Software Development Kits and Add on Plugins.
iNIS
(2017)
Grandhi Sai Anirudh
,
Soumya J.
Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes.
iNIS
(2017)
Sarfraz Hussain
,
Rajesh Kumar
,
Gaurav Trivedi
A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology.
iNIS
(2017)
Nawaz Shafi
,
Chitrakant Sahu
,
C. Periasamy
,
Jawar Singh
SiGe Source Charge Plasma TFET for Biosensing Applications.
iNIS
(2017)
Saurabh Chaturvedi
,
Mladen Bozanic
,
Saurabh Sinha
Implementation of a 6 GHz MEMS Switch.
iNIS
(2017)
Rathin Joshi
,
Rutu Parekh
,
Yash Agrawal
Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation.
iNIS
(2017)
Sitansusekhar Roymohapatra
,
Ganesh R. Gore
,
Akanksha Yadav
,
Mahesh B. Patil
,
Krishnan S. Rengrajan
,
Maryam Shojaei Baghini
Enhanced Look-Up Table Approach for Modeling of Floating Body SOI MOSFET.
iNIS
(2017)
Dharmendra Singh Yadav
,
Dheeraj Sharma
,
Sukeshni Tirkey
,
Deepak Soni
,
Deepak G. Sharma
,
Shriya Bajpai
,
Neeraj Sharma
A Comparative Study of GaP/SiGe Hetero Junction Double Gate Tunnel Field Effect Transistor.
iNIS
(2017)
Samya Muhuri
,
Debasree Das
,
Susanta Chakraborty
An Automated Game Theoretic Approach for Cooperative Road Traffic Management in Disaster.
iNIS
(2017)
Anoop D
,
Nithin Kumar Yernad Balachandra
,
Vasantha Moodabettu Harishchandra
High Performance Sense Amplifier Based Flip Flop for Driver Applications.
iNIS
(2017)
Aditya Japa
,
T. Nagateja
,
Ramesh Vaddi
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms.
iNIS
(2017)
Mannem Naga Sasikanth
,
Sashank Gambhira
,
Mrigank Sharad
Design Optimization of DSP for Wearable Biomedical Device.
iNIS
(2017)
Pankaj Kumar
,
Syed Samsuz Zaman
,
Manash Pratim Sarma
,
Ashok Ray
,
Gaurav Trivedi
Basic CMOS Gate Design by Mixed-Mode Analysis of Step-Channel TMDG-MOSFET.
iNIS
(2017)
S. Dinesh Kumar
,
Himanshu Thapliyal
Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks.
iNIS
(2017)
Dharmendra Kumar
,
Chintoo Kumar
,
Shipra Gautam
,
Debasis Mitra
Design of Practical Parity Generator and Parity Checker Circuits in QCA.
iNIS
(2017)
Tapan Chowdhury
,
Arijit Mukherjee
,
Susanta Chakraborty
An Efficient MapReduce-Based Adaptive K-Means Clustering for Large Dataset.
iNIS
(2017)
Subhendu Kumar Sahoo
,
Pramod Kumar Meher
Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio.
iNIS
(2017)
Anirban Sengupta
,
Dipanjan Roy
Mathematical Validation of HWT Based Lossless Image Compression.
iNIS
(2017)
Sudeendra Kumar K
,
Sauvagya Ranjan Sahoo
,
Abhishek Mahapatra
,
Ayas Kanta Swain
,
Kamala Kanta Mahapatra
Microprocessor Based Physical Unclonable Function.
iNIS
(2017)
Rahul Kurzekar
,
Hardik Arora
,
Rahul Shrestha
Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform.
iNIS
(2017)
Pallabi Sarkar
,
Anirban Sengupta
,
Santosh Rathlavat
,
Mrinal Kanti Naskar
A Firefly Algorithm Driven Approach for High Level Synthesis.
iNIS
(2017)
Rekib Uddin Ahmed
,
Prabir Saha
Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime.
iNIS
(2017)
Shrestha Bansal
,
Hemanta Kumar Mondal
,
Sri Harsha Gade
,
Sujay Deb
Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs.
iNIS
(2017)
Tuhin Subhra Das
,
Prasun Ghosal
MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture.
iNIS
(2017)
IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017
iNIS
(2017)