Nithin Kumar Yernad Balachandra

Publication Activity (10 Years)

Years Active: 2017-2021
Publications (10 Years): 12

Top Topics

Hardware Implementation

Electron Beam Lithography

Fault Tolerance

Top Venues

IET Image Process.

Microelectron. J.

Publications

Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9 (2021)
Siddharth Rajkumar Kala, Sushma Chandaka, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra, Edoardo Bonizzoni
6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process. IET Circuits Devices Syst. 14 (3) (2020)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
Design and implementation of image kernels using reversible logic gates. IET Image Process. 14 (16) (2020)
Prasad Vernekar, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability. ISVLSI (2019)
Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra
Two-Step Flash ADC Using Standard Cell Based Flash ADCs. iSES (2019)
Pradeep R., Siddharth R. K., Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
Process Corner Calibration for Standard Cell Based Flash ADC. iSES (2019)
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures. Wirel. Pers. Commun. 100 (2) (2018)
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
An energy-efficient fault-aware core mapping in mesh-based network on chip systems. J. Netw. Comput. Appl. 105 (2018)
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
Hardware implementation of fault tolerance NoC core mapping. Telecommun. Syst. 68 (4) (2018)
Naresh Kumar Reddy Becchu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
System level fault-tolerance core mapping and FPGA-based verification of NoC. Microelectron. J. 70 (2017)
Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra
High-performance and energy-efficient fault-tolerance core mapping in NoC. Sustain. Comput. Informatics Syst. 16 (2017)
Anoop D, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
High Performance Sense Amplifier Based Flip Flop for Driver Applications. iNIS (2017)