Siddharth R. K.

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 24

Top Topics

Analog To Digital Converter

Particle Swarm Optimization

Top Venues

Publications

K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 12 (2024)
R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. ISCAS (2023)
K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 11 (2023)
Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. VLSID (2023)
Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran
Approximate Three-Operand Binary Adder for Error-Resilient Applications. iSES (2023)
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. VLSI Design (2021)
Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. ISCAS (2021)
Shiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. ISVLSI (2021)
Nitish Kumar, Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC. iSES (2020)
Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.
A 1.8 V, Mode-Configurable Hybrid Smart ADC. iSES (2020)
Suraj Dohar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B.
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. ISVLSI (2020)
Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. IEEE Trans. Circuits Syst. (12) (2020)
Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. SN Comput. Sci. 1 (6) (2020)
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., M. H. Vasantha, Ramnath Kini
A 1.8 V Quadrature Phase LC Oscillator for 5G Applications. iSES (2020)
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., Vasantha M. H., Ramnath Kini
A Wideband 12 Phase Ring Oscillator for 5G Applications. MWSCAS (2020)
Sunil R., Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
An Asynchronous Analog to Digital Converter for Video Camera Applications. ISVLSI (2019)
Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra
Two-Step Flash ADC Using Standard Cell Based Flash ADCs. iSES (2019)
Pradeep R., Siddharth R. K., Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
Process Corner Calibration for Standard Cell Based Flash ADC. iSES (2019)
Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. ISCAS (2018)
Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. ISVLSI (2018)
Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar
Design of Area-Power-Delay Efficient Square Root Carry Select Adder. iSES (2018)
Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. ISVLSI (2017)
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI (2017)
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI (2016)