M. H. Vasantha

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 43

Top Topics

Analog To Digital Converter

Top Venues

Publications

K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 12 (2024)
R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. ISCAS (2023)
K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 11 (2023)
Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. ISCAS (2022)
P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithini Kumar
$\pm \, 0.5$ V, 254 $\upmu $W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit. Circuits Syst. Signal Process. 40 (5) (2021)
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. VLSI Design (2021)
K. G. Shreeharsha, Charudatta Korde, M. H. Vasantha, Y. B. Nithini Kumar
Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm. iSES (2021)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9 (2021)
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications. Integr. 81 (2021)
Shiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. ISVLSI (2021)
P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithini Kumar
A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications. IEEE Trans. Circuits Syst. II Express Briefs 68 (6) (2021)
Nitish Kumar, Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC. iSES (2020)
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi
Design of Approximate Booth Squarer for Error-Tolerant Computing. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha
Reversible Logic Implementation of Image Denoising for Grayscale Images. MWSCAS (2020)
Bipul Boro, Karri Manikantta Reddy, Nithin Y. B. Kumar, M. H. Vasantha
Approximate radix-8 Booth multiplier for low power and high speed applications. Microelectron. J. 101 (2020)
Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. IEEE Trans. Circuits Syst. (12) (2020)
Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. SN Comput. Sci. 1 (6) (2020)
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access 8 (2020)
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., M. H. Vasantha, Ramnath Kini
A 1.8 V Quadrature Phase LC Oscillator for 5G Applications. iSES (2020)
Sunil R., Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
An Asynchronous Analog to Digital Converter for Video Camera Applications. ISVLSI (2019)
Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra
Two-Step Flash ADC Using Standard Cell Based Flash ADCs. iSES (2019)
P. S. Veerendranath, Vivek Sharma, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
Current Conveyor based Novel Gyrator filter for Biomedical Sensor Applications. TENCON (2019)
Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. iSES (2018)
Purnima Kalekar, Prasad Vernekar, M. H. Vasantha, Y. B. Nithin Kumar, Edoardo Bonizzoni
A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications. IEEE SENSORS (2018)
Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha
Performance Enhancement of Split Length Compensated Operational Amplifiers. ISVLSI (2018)
Anirudha Pandey, Karri Manikantta Reddy, Praveen Yadav, Nithin Y. B. Kumar, M. H. Vasantha
Design and Analysis of Approximate Multipliers for Error-Tolerant Applications. iSES (2018)
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. TENCON (2018)
Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. ISCAS (2018)
Praveen Yadav, Anirudha Pandey, Karri Manikantta Reddy, K. J. Ravi Prasad, M. H. Vasantha, Nithin Y. B. Kumar
Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs. MWSCAS (2018)
Dhavala Shashidhar, Vivek Sharma, G. R. Prashanth, Nithin Y. B. Kumar, M. H. Vasantha
Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell. TENCON (2018)
Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. ISVLSI (2018)
P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. VLSI Design (2018)
Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar
Design of Area-Power-Delay Efficient Square Root Carry Select Adder. iSES (2018)
Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi
Design of Approximate Dividers for Error Tolerant Applications. MWSCAS (2018)
Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. ISVLSI (2017)
Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. ISVLSI (2017)
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI (2017)
Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT (2016)
A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. VLSI Design (2016)
B. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. ISVLSI (2016)
Saurabh B. Kaurati, Nithin Y. B. Kumar, Shivnarayan Patidar, M. H. Vasantha
Design and Implementation of Tunable Bandpass Filter for Biomedical Applications. iNIS (2016)
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI (2016)
S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. ISVLSI (2016)
Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha
Low power, high speed error tolerant multiplier using approximate adders. VDAT (2015)