Kumar Y. B. Nithin

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 15

Top Topics

Cmos Image Sensor

Top Venues

Publications

K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 12 (2024)
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. VLSI Design (2021)
Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.
A 1.8 V, Mode-Configurable Hybrid Smart ADC. iSES (2020)
Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha
Performance Enhancement of Split Length Compensated Operational Amplifiers. ISVLSI (2018)
Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. ISCAS (2018)
P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. VLSI Design (2018)
Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi
Design of Approximate Dividers for Error Tolerant Applications. MWSCAS (2018)
Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. ISVLSI (2017)
Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. ISVLSI (2017)
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI (2017)
Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT (2016)
A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. VLSI Design (2016)
B. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. ISVLSI (2016)
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI (2016)
S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. ISVLSI (2016)
Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha
Low power, high speed error tolerant multiplier using approximate adders. VDAT (2015)
Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti
Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators. VLSI Design (2013)
Kumar Y. B. Nithin, Hervé Caracciolo, Edoardo Bonizzoni, A. Parra, Franco Maloberti
A 1.96-mW, 2.6-MHz bandwidth discrete time quadrature band-pass ΣΔ modulator. ISCAS (2013)
Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti
Interference rejection in delay line based quadrature band-pass ΣΔ modulators. ISCAS (2012)
Aldo Pena-Perez, Kumar Y. B. Nithin, Edoardo Bonizzoni, Franco Maloberti
Slew-rate and Gain Enhancement in Two Stage Operational Amplifiers. ISCAS (2009)
Kumar Y. B. Nithin, Selçuk Talay, Franco Maloberti
Complex Cascaded Bandpass SigmaDelta ADC Design. ISCAS (2009)
Kumar Y. B. Nithin, Selçuk Talay, Franco Maloberti
On the design of band-pass quadrature ΣΔ modulators. APCCAS (2008)