Low power, high speed error tolerant multiplier using approximate adders.

Karri Manikantta Reddy Kumar Y. B. Nithin Dheeraj Sharma M. H. Vasantha

Published in: VDAT (2015)

Keyphrases

low power
error tolerant
high speed
graph matching
low cost
power consumption
power dissipation
logic circuits
cmos technology
vlsi circuits
subgraph isomorphism
real time
low power consumption
digital signal processing
gate array
feature vectors
pairwise
database systems
mixed signal
image processing
computer vision