Sithara Raveendran

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 15

Top Topics

Image Compression

Compression Algorithm

Top Venues

Publications

Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran
Approximate Three-Operand Binary Adder for Error-Resilient Applications. iSES (2023)
Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. ISCAS (2022)
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications. J. Circuits Syst. Comput. 30 (8) (2021)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9 (2021)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha
Reversible Logic Implementation of Image Denoising for Grayscale Images. MWSCAS (2020)
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors. IEEE Access 8 (2020)
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access 8 (2020)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
Design and implementation of image kernels using reversible logic gates. IET Image Process. 14 (16) (2020)
Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.
Design and Analysis of Energy Efficient Reversible Logic based Full Adder. MWSCAS (2019)
Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. iSES (2018)
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. TENCON (2018)
Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. ISED (2017)
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000. ISED (2017)
Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT (2016)
A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. VLSI Design (2016)