Pranose J. Edavoor

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 19

Top Topics

Encryption Algorithm

Top Venues

IET Image Process.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Gopal Raut, Pranose J. Edavoor, David Selvakumar, Ritambhara Thakur
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators. ISQED (2024)
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks. IEEE Trans. Very Large Scale Integr. Syst. 32 (4) (2024)
Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. VLSID (2023)
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval. IEEE Trans. Very Large Scale Integr. Syst. 31 (1) (2023)
Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. ISCAS (2022)
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar
A New Approach to the Design and Implementation of a Family of Multiplier Free Orthogonal Wavelet Filter Banks. IEEE Trans. Circuits Syst. Video Technol. 32 (4) (2022)
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications. J. Circuits Syst. Comput. 30 (8) (2021)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9 (2021)
Aswini K. Samantaray, Amol D. Rahulkar, Pranose J. Edavoor
A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction. Circuits Syst. Signal Process. 40 (11) (2021)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha
Reversible Logic Implementation of Image Denoising for Grayscale Images. MWSCAS (2020)
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors. IEEE Access 8 (2020)
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access 8 (2020)
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
Design and implementation of image kernels using reversible logic gates. IET Image Process. 14 (16) (2020)
Pranose J. Edavoor, Amol D. Rahulkar
Design and implementation of a novel low complexity symmetric orthogonal wavelet filter-bank. IET Image Process. 13 (5) (2019)
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. TENCON (2018)
Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. ISED (2017)
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000. ISED (2017)
Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT (2016)
K. Jayasree, B. Naresh Kumar Reddy, B. Srinuvasu Kumar, J. V. N. Ramesh, Pranose J. Edavoor, Mohd Kashif Zia Ansari
Poster: An Efficient Low Power & High Performance in MPSOC. WCI (2015)
B. Naresh Kumar Reddy, N. Suresh, J. V. N. Ramesh, T. Pavithra, Y. Krupa Bahulya, Pranose J. Edavoor, S. Janaki Ram
An efficient approach for design and testing of FPGA programming using Lab VIEW. ICACCI (2015)