Aneesh Raveendran

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 7

Top Topics

Data Conversion

Instruction Set

Parallel Processors

Top Venues

Publications

Pranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. VLSID (2023)
Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. VLSI Design (2021)
Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine
PositGen-A Verification Suite for Posit Arithmetic. VLSI Design (2021)
Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. VLSI Design (2020)
Vivian Desalphine, Somya Dashora, Laxita Mali, Suhas K, Aneesh Raveendran, David Selvakumar
Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA. VDAT (2020)
Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. VDAT (2019)
Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. David Selvakumar
RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. VDAT (2019)
Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, Vivian Desalphine
Out of order floating point coprocessor for RISC V ISA. VDAT (2015)
Aneesh Raveendran, Vinayak Patil, Vivian Desalphine, P. M. Sobha, A. David Selvakumar
RISC-V out-of-order data conversion co-processor. VDAT (2015)