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Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU.
Aneesh Raveendran
Vinay Kumar
Vivian Desalphine
David Selvakumar
Published in:
VDAT (2019)
Keyphrases
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parallel implementation
instruction set
floating point
high level language
floating point arithmetic
application specific
floating point unit
fixed point
computer architecture
level parallelism
real time
database systems
low cost
parallel algorithm
embedded systems