Devesh Dwivedi

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 10

Top Topics

Efficient Computation

Top Venues

Circuits Syst. Signal Process.

Publications

Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS (2023)
Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. VLSID (2023)
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications. Integr. 81 (2021)
Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi
Design of Approximate Booth Squarer for Error-Tolerant Computing. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38 (4) (2019)
Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi
Design of Approximate Dividers for Error Tolerant Applications. MWSCAS (2018)
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications. Circuits Syst. Signal Process. 35 (2) (2016)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35 (9) (2016)
C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan
A robust 8T FinFET SRAM cell with improved stability for low voltage applications. VDAT (2016)
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations. Microelectron. J. 51 (2016)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi
SRAM Using FinFET. ACM Great Lakes Symposium on VLSI (2015)
Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity. iNIS (2015)
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
Single-ended sub-threshold finfet 7T SRAM cell without boosted supply. ICICDT (2014)
Devesh Dwivedi, Suman Dwivedi, Eswararao Potladhurthi
Voltage up level shifter with improved performance and reduced power. CCECE (2012)