Vikas Vijayvargiya

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 7

Top Topics

Random Access Memory

Semiconductor Devices

Parameter Values

Top Venues

Circuits Syst. Signal Process.

J. Low Power Electron.

Publications

Aruna Kumari Neelam, V. Bharath Sreenivasulu, Vikas Vijayvargiya, Abhishek Kumar Upadhyay, J. Ajayan, M. Uma
Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective. IEEE Access 12 (2024)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38 (4) (2019)
Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integr. 62 (2018)
Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma
Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. J. Low Power Electron. 13 (1) (2017)
Bhupendra Singh Reniwal, P. Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSI Design (2017)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35 (9) (2016)
Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav, Santosh Kumar Vishvakarma
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. iNIS (2016)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi
SRAM Using FinFET. ACM Great Lakes Symposium on VLSI (2015)
Neha Jagwani, Vikas Vijayvargiya, Santosh Kumar Vishvakarma
Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. iNIS (2015)