Santosh Kumar Vishvakarma

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 62

Top Topics

Activation Function

Top Venues

Circuits Syst. Signal Process.

Microelectron. J.

Publications

Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar
QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit. IEEE Access 12 (2024)
Sudheer Vishwakarma, Gopal Raut, Sonu Jaiswal, Santosh Kumar Vishvakarma, Dhruva Ghai
A Precision-Aware Neuron Engine for DNN Accelerators. SN Comput. Sci. 5 (5) (2024)
Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma
In-Memory Computing with 6T SRAM for Multi-operator Logic Design. Circuits Syst. Signal Process. 43 (1) (2024)
Narendra Singh Dhakad, Santosh Kumar Vishvakarma
Configurable Multi-Port Memory Architecture for High-Speed Data Communication. CoRR (2024)
Narendra Singh Dhakad, Yuvnish Malhotra, Santosh Kumar Vishvakarma, Kaushik Roy
SHA-CNN: Scalable Hierarchical Aware Convolutional Neural Network for Edge AI. CoRR (2024)
Kavitha Soundrapandiyan, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (1) (2023)
Vasundhara Trivedi, Khushbu Lalwani, Gopal Raut, Avikshit Khomane, Neha Ashar, Santosh Kumar Vishvakarma
Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs. Circuits Syst. Signal Process. 42 (12) (2023)
Mohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application. VLSID (2023)
Gopal Raut, Saurabh Karkun, Santosh Kumar Vishvakarma
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16 (3) (2023)
Sumiran Mehra, Gopal Raut, Ribhu Das Purkayastha, Santosh Kumar Vishvakarma, Anton Biasizzo
An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning. IEEE Access 11 (2023)
Gopal Raut, Jogesh Mukala, Vishal Sharma, Santosh Kumar Vishvakarma
Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. Circuits Syst. Signal Process. 42 (10) (2023)
Ravi Kumar, Rajasekhar Nagulapalli, Santosh Kumar Vishvakarma
A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency. J. Circuits Syst. Comput. 32 (4) (2023)
Gunjan Rajput, V. Logashree, Kunika Naresh Biyani, Santosh Kumar Vishvakarma
Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators. Circuits Syst. Signal Process. 42 (10) (2023)
Sudheer Vishwakarma, Gopal Raut, Narendra Singh Dhakad, Santosh Kumar Vishvakarma, Dhruva Ghai
A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators. IFIPIoT (1) (2023)
Ravi Kumar, Pooja Bohara, Krishna Thakur, Santosh Kumar Vishvakarma
A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic. J. Circuits Syst. Comput. 32 (4) (2023)
Varun Bhatnagar, Gopal Raut, Santosh Kumar Vishvakarma
Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array. ACM Great Lakes Symposium on VLSI (2022)
Harsh Chhajed, Gopal Raut, Narendra Singh Dhakad, Sudheer Vishwakarma, Santosh Kumar Vishvakarma
BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator. Circuits Syst. Signal Process. 41 (4) (2022)
Gunjan Rajput, Shashank Agrawal, Gopal Raut, Santosh Kumar Vishvakarma
An accurate and noninvasive skin cancer screening based on imaging technique. Int. J. Imaging Syst. Technol. 32 (1) (2022)
Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. ISVLSI (2022)
Gopal Raut, Anton Biasizzo, Narendra Singh Dhakad, Neha Gupta, Gregor Papa, Santosh Kumar Vishvakarma
Data multiplexed and hardware reused architecture for deep neural network accelerator. Neurocomputing 486 (2022)
Gunjan Rajput, Kunika Naresh Biyani, V. Logashree, Santosh Kumar Vishvakarma
SCAN: Streamlined Composite Activation Function Unit for Deep Neural Accelerators. Circuits Syst. Signal Process. 41 (6) (2022)
Gunjan Rajput, Shashank Agrawal, Kunika Naresh Biyani, Santosh Kumar Vishvakarma
Early breast cancer diagnosis using cogent activation function-based deep learning implementation on screened mammograms. Int. J. Imaging Syst. Technol. 32 (4) (2022)
S. Kavitha, Santosh Kumar Vishvakarma, B. S. Reniwal
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. VDAT (2022)
Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, Soumya J., M. B. Srinivas, Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi
Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. COMSNETS (2021)
Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar
RECON: Resource-Efficient CORDIC-Based Neuron Architecture. IEEE Open J. Circuits Syst. 2 (2021)
Gunjan Rajput, Gopal Raut, Mahesh Chandra, Santosh Kumar Vishvakarma
VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators. Microprocess. Microsystems 84 (2021)
Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. ACM Great Lakes Symposium on VLSI (2021)
Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar
A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies. IEEE Access 9 (2021)
Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar
Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture". IEEE Open J. Circuits Syst. 2 (2021)
Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma
A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application. J. Circuits Syst. Comput. 29 (7) (2020)
Mahesh Kumawat, Abhishek Kumar Upadhyay, Sanjay Sharma, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma
An improved current mode logic latch for high-speed applications. Int. J. Commun. Syst. 33 (13) (2020)
Gopal Raut, Ambika Prasad Shah, Vishal Sharma, Gunjan Rajput, Santosh Kumar Vishvakarma
A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture. Circuits Syst. Signal Process. 39 (9) (2020)
Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar
A CORDIC Based Configurable Activation Function for ANN Applications. ISVLSI (2020)
Ambika Prasad Shah, Santosh Kumar Vishvakarma, Michael Hübner
Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications. J. Electron. Test. 36 (2) (2020)
Neha Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, Santosh Kumar Vishvakarma
Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell. VDAT (2019)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38 (4) (2019)
Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. VDAT (2019)
Neha Gupta, Jitesh Prasad, Rana Sagar Kumar, Gunjan Rajput, Santosh Kumar Vishvakarma
A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell. VDAT (2019)
Ankur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications. VDAT (2019)
Sajid Khan, Ambika Prasad Shah, Neha Gupta, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma
An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. Microelectron. J. 92 (2019)
Sajid Khan, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma
Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. VDAT (2019)
Prachi Sanvale, Neha Gupta, Vaibhav Neema, Ambika Prasad Shah, Santosh Kumar Vishvakarma
An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network. Microelectron. J. 92 (2019)
Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma
SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit. IET Comput. Digit. Tech. 13 (3) (2019)
Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma
An Ultra Low Power AES Architecture for IoT. VDAT (2019)
Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma, Palagani Yellappa, Jun Rim Choi, Ramesh Vaddi
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. ISCAS (2018)
Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma, Abhijit Karmakar, Raj Singh
A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. VDAT (2018)
Pooran Singh, Santosh Kumar Vishvakarma
Ultra-Low Power High Stability 8T SRAM for Application in Object Tracking System. IEEE Access 6 (2018)
S. Mishra, Pandurang S. Londhe, Mohan Santhakumar, Santosh Kumar Vishvakarma, B. M. Patre
Robust task-space motion control of a mobile manipulator using a nonlinear control with an uncertainty estimator. Comput. Electr. Eng. 67 (2018)
Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integr. 62 (2018)
Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma
A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. VDAT (2018)
Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma
An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells. Microelectron. Reliab. 87 (2018)
Vishal Sharma, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan, Kari Halonen
A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes. Int. J. Circuit Theory Appl. 46 (12) (2018)
Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma
Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. J. Low Power Electron. 13 (1) (2017)
Ambika Prasad Shah, Nandakishor Yadav, Santosh Kumar Vishvakarma
LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits. VDAT (2017)
Bhupendra Singh Reniwal, Praneet Bhatia, Santosh Kumar Vishvakarma
Design and investigation of variability aware sense amplifier for low power, high speed SRAM. Microelectron. J. 59 (2017)
Bhupendra Singh Reniwal, P. Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSI Design (2017)
Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma
Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET. iNIS (2016)
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications. Circuits Syst. Signal Process. 35 (2) (2016)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35 (9) (2016)
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations. Microelectron. J. 51 (2016)
Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav, Santosh Kumar Vishvakarma
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. iNIS (2016)
C. B. Kushwah, Santosh Kumar Vishvakarma
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Praneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. VDAT (2015)
Dheeraj Sharma, Santosh Kumar Vishvakarma
Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron. J. 46 (8) (2015)
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi
SRAM Using FinFET. ACM Great Lakes Symposium on VLSI (2015)
Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity. iNIS (2015)
Neha Jagwani, Vikas Vijayvargiya, Santosh Kumar Vishvakarma
Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. iNIS (2015)
C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
Single-ended sub-threshold finfet 7T SRAM cell without boosted supply. ICICDT (2014)
C. B. Kushwah, Santosh Kumar Vishvakarma
A sub-threshold eight transistor (8T) SRAM cell design for stability improvement. ICICDT (2014)
Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM. VDAT (2013)
Dheeraj Sharma, Santosh Kumar Vishvakarma
Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions. Microelectron. J. 43 (6) (2012)
Chandrabhan Kushwah, Santosh Kumar Vishvakarma
Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin. VDAT (2012)
Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta
) symmetric double gate MOSFET. Microelectron. J. 42 (5) (2011)