M. B. Srinivas

ORCID

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 36

Top Venues

VLSI Design

SoCC

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Harshiv Chandra, Akash Ghosh, Rahul Singh, M. B. Srinivas
SNN-LIF Model for Glaucoma Classification. AICAS (2024)
Khushi Gupta, Arshdeep Singh, Sreenivasa Reddy Yeduri, M. B. Srinivas, Linga Reddy Cenkeramaddi
Hand gestures recognition using edge computing system based on vision transformer and lightweight CNN. J. Ambient Intell. Humaniz. Comput. 14 (3) (2023)
P. Sai Phaneendra, Chetan Vudadha, M. B. Srinivas
Optimization of Reversible Circuits Using Gate Pair Classification. SN Comput. Sci. 3 (1) (2022)
Mahesh Kumar Adimulam, M. B. Srinivas
A 12-bit, 1.1-GS/s, Low-Power Flash ADC. IEEE Trans. Very Large Scale Integr. Syst. 30 (3) (2022)
Diyanesh Chinnakkonda, Karthick Rajamani, M. B. Srinivas
Architecture slack exploitation for phase classification and performance estimation in server-class processors. J. Parallel Distributed Comput. 169 (2022)
Saravanan Sethuraman, Venkata Kalyan Tavva, M. B. Srinivas
Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (9) (2022)
Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, Soumya J., M. B. Srinivas, Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi
Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. COMSNETS (2021)
Himanshu Thapliyal, Katina Michael, Saraju P. Mohanty, M. B. Srinivas, Madhavi K. Ganapathiraju
Consumer Technology-Based Solutions for COVID-19. IEEE Consumer Electron. Mag. 10 (2) (2021)
Kotturi Venkata SaiTeja, Ponduru Manoj Kumar, Punnamraju Sarath Chandra, N. K. Jisy, Md. Hasnat Ali, M. B. Srinivas
'Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus Images by Combining Random Walk Algorithm with Otsu Thresholding'. NER (2021)
Saravanan Sethuraman, Venkata Kalyan Tavva, Karthick Rajamani, Chitra K. Subramanian, Kyu-hyoun Kim, Hillery C. Hunter, M. B. Srinivas
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Veeresh Babu Vulligaddala, Sandeep Vernekar, Sudhakar Singamala, Ravi Kumar Adusumalli, Vijay Ele, Manfred Brandl, M. B. Srinivas
A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles. IEEE Trans. Ind. Informatics 16 (5) (2020)
Avinash S. Vaidya, M. B. Srinivas
A frequency domain beamspace adaptive receive beamformer for ultrasound imaging systems: phantom simulation results. Signal Image Video Process. 13 (3) (2019)
Goutham Makkena, M. B. Srinivas
Levin's Transformation-based Continuous-Time Linear-Phase Selective Filters. Circuits Syst. Signal Process. 38 (11) (2019)
Syed Ershad Ahmed, M. B. Srinivas
An Improved Logarithmic Multiplier for Media Processing. J. Signal Process. Syst. 91 (6) (2019)
Chetan Vudadha, Ajay Surya, Saurabh Agrawal, M. B. Srinivas
Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Linga Reddy Cenkeramaddi, Ashish Goyal, Asheesh Bhuria, M. B. Srinivas, Soumya J.
Design of Software and Data Analytics for Self-Powered Wireless IoT Devices. iSES (2018)
Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas
Improved designs of digit-by-digit decimal multiplier. Integr. 61 (2018)
Goutham Makkena, M. B. Srinivas
Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter Approximation. Circuits Syst. Signal Process. 37 (3) (2018)
Chetan Vudadha, M. B. Srinivas
Design Methodologies for Ternary Logic Circuits. ISMVL (2018)
Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni, M. B. Srinivas
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. VLSI Design (2018)
Veeresh Babu Vulligaddala, Ravikumar Adusumalli, Sudhakar Singamala, M. B. Srinivas
A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application. IEEE J. Solid State Circuits 53 (10) (2018)
Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas
Energy efficient design of CNFET-based multi-digit ternary adders. Microelectron. J. 75 (2018)
Mahesh Kumar Adimulam, Adimulam Divya, K. Tejaswi, M. B. Srinivas
A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements. EMBC (2017)
Mahesh Kumar Adimulam, Krishna Kumar Movva, M. B. Srinivas
A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications. SoCC (2017)
Mahesh Kumar Adimulam, M. B. Srinivas
Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare System. MobiHealth (2017)
Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas
An ESOP Based Cube Decomposition Technique for Reversible Circuits. RC (2017)
Mahesh Kumar Adimulam, Krishna Kumar Movva, Amit Kapoor, M. B. Srinivas
A low power, programmable bias inverter quantizer (BIQ) flash ADC. VLSI-SoC (2017)
Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas
Optimizing the Reversible Circuits Using Complementary Control Line Transformation. RC (2017)
Mahesh Kumar Adimulam, Krishna Kumar Movva, K. Kolluru, M. B. Srinivas
A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications. ISVLSI (2017)
Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas
A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp. VLSI Design (2017)
M. B. Srinivas
T2A: Analog and RF circuits. SoCC (2017)
Mahesh Kumar Adimulam, M. B. Srinivas
Modeling of EXG (ECG, EMG and EEG) non-idealities using MATLAB. CISP-BMEI (2016)
Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. iNIS (2016)
Rakhee, M. B. Srinivas
A Soft Computing Approach for Data Routing in Hospital Area Networks (HAN). Int. J. Bus. Data Commun. Netw. 12 (2) (2016)
Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas
A Hybrid Energy Efficient Digital Comparator. VLSI Design (2016)
Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas
An Iterative Logarithmic Multiplier with Improved Precision. ARITH (2016)
Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. VLSI Design (2014)
B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. VLSI Design (2014)
P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas
An Optimized Design of Reversible Quantum Comparator. VLSI Design (2014)
Abhilash K. N, M. B. Srinivas
modulator with high-level sizing and power estimation. SoCC (2014)
Avinash S. Vaidya, T. S. L. Radhika, M. B. Srinivas, Mannan Mridha
Estimation of Arterial Stiffness through Pulse Transit Time Measurement. BIODEVICES (2014)
Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed, M. B. Srinivas
A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits. APCCAS (2014)
Goutham Makkena, Prabhakara Rao, M. B. Srinivas
Uniform approximation of Gaussian wavelet for biomedical signal processing in analog domain. EMBC (2013)
Avinash S. Vaidya, M. B. Srinivas, P. Himabindu, Daria Jumaxanova
A smart phone/tablet based mobile health care system for developing countries. EMBC (2013)
Chetan Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas
CNFET based ternary magnitude comparator. ISCIT (2012)
Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design (2012)
Santosh Kumar Jena, M. B. Srinivas
On the Suitability of Multi-Core Processing for Embedded Automotive Systems. CyberC (2012)
Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Modified Twin Precision Multiplier with 2D Bypassing Technique. ISED (2012)
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. ISED (2011)
Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Prefix Based Reconfigurable Adder. ISVLSI (2011)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD (2011)
P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT (2011)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED (2011)
Gudipati Kalyan, M. B. Srinivas
An efficient ODT calibration scheme for improved signal integrity in memory interface. APCCAS (2010)
Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electron. 6 (3) (2010)
Pradeep Jamwal, M. B. Srinivas, G. V. K. Sarma, M. Murali Krishna
A new approach to minimize leakage power in nano-scale VLSI adder. ICWET (2010)
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI (2010)
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI (2010)
Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design (2010)
Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas
Efficient Reversible Logic Design of BCD Subtractors. Trans. Comput. Sci. 3 (2009)
Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas
A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI (2009)
Vasanth Iyer, S. Sitharama Iyengar, Garimella Rama Murthy, Bertrand Hochet, Vir V. Phoha, M. B. Srinivas
Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks. IWCMC (2009)
Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas
Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design (2009)
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electron. 5 (3) (2009)
Swathi Ramasahayam, M. B. Srinivas
All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. ISVLSI (2009)
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
A novel low power, variable resolution pipelined ADC. SoCC (2009)
Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design (2008)
J. V. R. Ravindra, M. B. Srinivas
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI (2008)
Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ISQED (2008)
Vasanth Iyer, Rammurthy Garimella, M. B. Srinivas
Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks. SUTC (2008)
Lingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. ISVLSI (2008)
K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. ISVLSI (2007)
Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas
Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio. GLOBECOM (2007)
Sudhakar Maddi, M. B. Srinivas
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. SBCCI (2007)
Keerthi Laal Kala, M. B. Srinivas
Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction. FOCI (2007)
J. V. R. Ravindra, M. B. Srinivas
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. DSD (2007)
M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas
New and Improved Architectures for Montgomery Modular Multiplication. Mob. Networks Appl. 12 (4) (2007)
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS (2007)
Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. ACM Great Lakes Symposium on VLSI (2007)
Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas
A Comparative Study of Different FFT Architectures for Software Defined Radio. SAMOS (2007)
J. V. R. Ravindra, M. B. Srinivas
Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. Nano-Net (2007)
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design (2007)
J. V. R. Ravindra, M. B. Srinivas
Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. J. Circuits Syst. Comput. 16 (6) (2007)
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI (2007)
Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas
Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI (2007)
K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas
Bus encoding schemes for minimizing delay in VLSI interconnects. SBCCI (2007)
M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). VLSI Design (2007)
M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. VLSI-SoC (2007)
Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). ISCAS (2007)
Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). DSD (2006)
Ramachandruni Venkata Kamala, M. B. Srinivas
High-Throughput Montgomery Modular Multiplication. VLSI-SoC (2006)
K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. DELTA (2006)
K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. ISCAS (2006)
Himanshu Thapliyal, M. B. Srinivas
A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits CoRR (2006)
Himanshu Thapliyal, M. B. Srinivas
Novel Reversible Multiplier Architecture Using Reversible TSG Gate. AICCSA (2006)
Himanshu Thapliyal, M. B. Srinivas
Novel Reversible Multiplier Architecture Using Reversible TSG Gate CoRR (2006)
Himanshu Thapliyal, M. B. Srinivas
Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU CoRR (2006)
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. VLSI Design (2006)
Himanshu Thapliyal, M. B. Srinivas
The New BCD Subtractor and Its Reversible Logic Implementation. Asia-Pacific Computer Systems Architecture Conference (2006)
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format CoRR (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

M. B. Srinivas