P. Sai Phaneendra

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 2

Top Topics

Design Methodologies

Top Venues

Publications

P. Sai Phaneendra, Chetan Vudadha, M. B. Srinivas
Optimization of Reversible Circuits Using Gate Pair Classification. SN Comput. Sci. 3 (1) (2022)
Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. iNIS (2016)
P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas
An Optimized Design of Reversible Quantum Comparator. VLSI Design (2014)
Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED (2014)
Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI (2012)
Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI (2012)
Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design (2012)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD (2011)
P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT (2011)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED (2011)