Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
P. Sai PhaneendraChetan VudadhaSyed Ershad AhmedSreehari VeeramachaneniN. Moorthy MuthukrishnanM. B. SrinivasPublished in: ISCIT (2011)
Keyphrases
- power reduction
- high speed
- rate distortion
- low complexity
- bit rate
- power consumption
- b tree
- low power
- video codec
- analog circuits
- priority queue
- error control
- video compression
- preemptive scheduling
- delay insensitive
- electronic circuits
- higher priority
- circuit design
- data sets
- motion estimation
- evolutionary algorithm
- computer vision