Sreehari Veeramachaneni

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 19

Top Topics

Energy Efficient

Video Processing

Top Venues

Int. J. Circuit Theory Appl.

Publications

Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad
Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems. VLSID (2024)
L. Hemanth Krishna, Ayesha Sk, J. Bhaskara Rao, Sreehari Veeramachaneni, Sk. Noor Mahammad
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor. IEEE Embed. Syst. Lett. 16 (2) (2024)
Rishi Agrawal, Narayanabhatla Savyasachi Abhijith, Uppugunduru Anil Kumar, Sreehari Veeramachaneni, Syed Ershad Ahmed
Energy-Efficient Ternary Multiplier. AICAS (2024)
Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs. Integr. 93 (2023)
Sangireddy Tharuni, Basani Harshavardhan Reddy, Bhukya Mamatha, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni
Power Efficient Approximate Ternary Subtractor for Image Processing Applications. iSES (2023)
Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni, Syed Ershad Ahmed
Design of Energy Efficient Posit Multiplier. ACM Great Lakes Symposium on VLSI (2023)
Raghavendra Kumar Sakali, P. Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Sk. Noor Mahammad
Optimized Fault-Tolerant Adder Design Using Error Analysis. J. Circuits Syst. Comput. 32 (6) (2023)
Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad
Logic Locking Designs at Transistor Level for Full Adders. iSES (2022)
L. Guna Sekhar Sai Harsha, Bhaskara Rao Jammu, Nalini Bodasingi, Sreehari Veeramachaneni, Noor Mohammad S.
A Low Error, Hardware Efficient Logarithmic Multiplier. Circuits Syst. Signal Process. 41 (1) (2022)
Chinthalgiri Jyothi, K. Saranya, Bhaskara Rao Jammu, Sreehari Veeramachaneni, Sk. Noor Mahammad
A New Approximate 4-2 Compressor using Merged Sum and Carry. J. Electron. Test. 38 (4) (2022)
Bhaskara Rao Jammu, L. Guna Sekhar Sai Harsha, Nalini Bodasingi, Sreehari Veeramachaneni, Noor Mohammad S.
Hardware efficient circuit for low error logarithmic converter. J. Comput. Methods Sci. Eng. 22 (2) (2022)
L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad
Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications. iSES (2021)
Y. Mounica, K. Naresh Kumar, Sreehari Veeramachaneni, S. K. Noor Mahammad
Energy efficient signed and unsigned radix 16 booth multiplier design. Comput. Electr. Eng. 90 (2021)
Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad
Design and Analysis of Obfuscated Full Adders. ICM (2021)
L. Hemanth Krishna, Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, S. K. Noor Mahammad
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication. IET Comput. Digit. Tech. 15 (1) (2021)
L. Guna Sekhar Sai Harsha, Bhaskara Rao Jammu, Visweswara Rao Samoju, Sreehari Veeramachaneni, Noor Mohammad S.
A low-error, memory-based fast binary antilogarithmic converter. Int. J. Circuit Theory Appl. 49 (7) (2021)
L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, S. K. Noor Mahammad
Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications. ICECS (2021)
Chandana Mounica, Sagar Krishna, Sreehari Veeramachaneni, Sk. Noor Mahammad
Efficient implementation of mixed-precision multiply-accumulator unit for AI algorithms. Int. J. Circuit Theory Appl. 48 (8) (2020)
Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni, M. B. Srinivas
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. VLSI Design (2018)
B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. VLSI Design (2014)
P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas
An Optimized Design of Reversible Quantum Comparator. VLSI Design (2014)
Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED (2014)
Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI (2012)
Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI (2012)
Chetan Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas
CNFET based ternary magnitude comparator. ISCIT (2012)
Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design (2012)
Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Modified Twin Precision Multiplier with 2D Bypassing Technique. ISED (2012)
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. ISED (2011)
Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Prefix Based Reconfigurable Adder. ISVLSI (2011)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD (2011)
P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT (2011)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED (2011)
Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electron. 6 (3) (2010)
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Low power, variable resolution pipelined analog to Digital converter with sub flash architecture. APCCAS (2010)
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI (2010)
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI (2010)
Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design (2010)
Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas
A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI (2009)
Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas
Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design (2009)
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electron. 5 (3) (2009)
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
A novel low power, variable resolution pipelined ADC. SoCC (2009)
Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design (2008)
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS (2007)
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design (2007)
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI (2007)
Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas
Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI (2007)