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Bhaskara Rao Jammu
ORCID
Publication Activity (10 Years)
Years Active: 2021-2022
Publications (10 Years): 6
Top Topics
Low Error
Top Venues
Int. J. Circuit Theory Appl.
J. Comput. Methods Sci. Eng.
J. Electron. Test.
Circuits Syst. Signal Process.
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Publications
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L. Guna Sekhar Sai Harsha
,
Bhaskara Rao Jammu
,
Nalini Bodasingi
,
Sreehari Veeramachaneni
,
Noor Mohammad S.
A Low Error, Hardware Efficient Logarithmic Multiplier.
Circuits Syst. Signal Process.
41 (1) (2022)
Nalini Bodasingi
,
Balaji Narayanam
,
Bhaskara Rao Jammu
Automatic diagnosis of pneumonia using backward elimination method based SVM and its hardware implementation.
Int. J. Imaging Syst. Technol.
32 (3) (2022)
Chinthalgiri Jyothi
,
K. Saranya
,
Bhaskara Rao Jammu
,
Sreehari Veeramachaneni
,
Sk. Noor Mahammad
A New Approximate 4-2 Compressor using Merged Sum and Carry.
J. Electron. Test.
38 (4) (2022)
Bhaskara Rao Jammu
,
L. Guna Sekhar Sai Harsha
,
Nalini Bodasingi
,
Sreehari Veeramachaneni
,
Noor Mohammad S.
Hardware efficient circuit for low error logarithmic converter.
J. Comput. Methods Sci. Eng.
22 (2) (2022)
Chitlu Subhasri
,
Bhaskara Rao Jammu
,
L. Guna Sekhar Sai Harsha
,
Nalini Bodasingi
,
Visweswara Rao Samoju
Hardware-efficient approximate logarithmic division with improved accuracy.
Int. J. Circuit Theory Appl.
49 (1) (2021)
L. Guna Sekhar Sai Harsha
,
Bhaskara Rao Jammu
,
Visweswara Rao Samoju
,
Sreehari Veeramachaneni
,
Noor Mohammad S.
A low-error, memory-based fast binary antilogarithmic converter.
Int. J. Circuit Theory Appl.
49 (7) (2021)