Subhankar Pal

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 28

Top Topics

Matrix Multiplication

Reconfigurable Architecture

Autonomous Vehicles

Top Venues

IEEE J. Solid State Circuits

Publications

Tapan Jana, Subhankar Pal, Amit Shaw, L. S. Ramachandra
A remedy to mitigate tensile instability in SPH for simulating large deformation and failure of geomaterials. CoRR (2024)
Yongmo Park, Subhankar Pal, Aporva Amarnath, Karthik Swaminathan, Wei D. Lu, Alper Buyuktosunoglu, Pradip Bose
Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms. IEEE Comput. Archit. Lett. 23 (1) (2024)
Ehud Aharoni, Moran Baruch, Pradip Bose, Alper Buyuktosunoglu, Nir Drucker, Subhankar Pal, Tomer Pelleg, Kanthi K. Sarpatwar, Hayim Shaul, Omri Soceanu, Roman Vaculín
Efficient Pruning for Machine Learning Under Homomorphic Encryption. ESORICS (4) (2023)
Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher. CoRR (2023)
Mohammad Ali Khoshkholghi, Toktam Mahmoodi, Subhankar Pal, Subhash Chopra, Mayuri Tendulkar, Sandip Sarkar
xURLCC in 6g with meshed RAN. CoRR (2023)
Aporva Amarnath, Subhankar Pal, Hiwot Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald G. Dreslinski, Pradip Bose
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs. CoRR (2022)
Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
A Holistic Solution for Reliability of 3D Parallel Systems. ACM J. Emerg. Technol. Comput. Syst. 18 (1) (2022)
Ehud Aharoni, Moran Baruch, Pradip Bose, Alper Buyuktosunoglu, Nir Drucker, Subhankar Pal, Tomer Pelleg, Kanthi K. Sarpatwar, Hayim Shaul, Omri Soceanu, Roman Vaculín
HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion. CoRR (2022)
Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators. ACM Trans. Embed. Comput. Syst. 21 (6) (2022)
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits 57 (4) (2022)
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. CoRR (2021)
Subhankar Pal, Aporva Amarnath, Siying Feng, Michael F. P. O'Boyle, Ronald G. Dreslinski, Christophe Dubach
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator. MICRO (2021)
Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators. ISPASS (2021)
Aporva Amarnath, Subhankar Pal, Hiwot Tadese Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald Dreslinski Jr., Pradip Bose
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles. IEEE Comput. Archit. Lett. 20 (2) (2021)
Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics. DAC (2021)
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. VLSI Circuits (2021)
Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
R2D3: A Reliability Engine for 3D Parallel Systems. DAC (2020)
Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael F. P. O'Boyle, Trevor N. Mudge, Ronald G. Dreslinski
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework. IISWC (2020)
A. Soorishetty, Jian Zhou, Subhankar Pal, David T. Blaauw, H. Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture. ICASSP (2020)
Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge
Sparse-TPU: adapting systolic arrays for sparse matrices. ICS (2020)
Subhankar Pal, Siying Feng, Dong-Hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael F. P. O'Boyle, Murray Cole, Chaitali Chakrabarti, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration. PACT (2020)
Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. IEEE J. Solid State Circuits 55 (4) (2020)
Yan Xiong, Jian Zhou, Subhankar Pal, David T. Blaauw, H. S. Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture. ISCAS (2020)
Augusto Vega, Aporva Amarnath, John-David Wellman, Hiwot Kassa, Subhankar Pal, Hubertus Franke, Alper Buyuktosunoglu, Ronald G. Dreslinski, Pradip Bose
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors. CoRR (2020)
Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. VLSI Circuits (2019)
Siying Feng, Subhankar Pal, Yichen Yang, Ronald G. Dreslinski
Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective. ISPASS (2019)
Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator. HPCA (2018)
Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski
A carbon nanotube transistor based RISC-V processor using pass transistor logic. ISLPED (2017)
Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED (2014)