Morteza Fayazi

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 17

Top Topics

Analog Circuits

Open Information Extraction

Memory Hierarchy

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Serafina Kamp, Morteza Fayazi, Zineb Benameur-El Youbi, Shuyan Yu, Ronald G. Dreslinski
Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications. CoRR (2023)
Morteza Fayazi, Morteza Tavakoli Taba, Ehsan Afshari, Ronald G. Dreslinski
AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (11) (2023)
Morteza Tavakoli Taba, S. M. Hossein Naghavi, Morteza Fayazi, Ali Sadeghi, Andreia Cathelin, Ehsan Afshari
A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging. CICC (2023)
Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. CoRR (2023)
Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. ICCAD (2023)
Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski
Tablext: A combined neural network and heuristic based table extractor. Array 15 (2022)
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits 57 (4) (2022)
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. VLSI Technology and Circuits (2022)
Morteza Fayazi, Zachary Colter, Zineb Benameur-El Youbi, Javad Bagherzadeh, Tutu Ajayi, Ronald G. Dreslinski
FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. CoRR (2021)
Morteza Fayazi, Zachary Colter, Ehsan Afshari, Ronald G. Dreslinski
Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (6) (2021)
Zach Colter, Morteza Fayazi, Zineb Benameur-El, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski
Tablext: A Combined Neural Network And Heuristic Based Table Extractor. CoRR (2021)
Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. VLSI Circuits (2021)
Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. VLSI-SoC (Selected Papers) (2020)
Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff
An Open-source Framework for Autonomous SoC Design with Analog Block Generation. VLSI-SOC (2020)
Morteza Fayazi, Ali Fotowat, Zahra Kavehvash
A Simplified Approach to Two-Port Analysis in Feedback. CoRR (2019)
Morteza Fayazi, Jafar Hasani
Structural relations between brain-behavioral systems, social anxiety, depression and internet addiction: With regard to revised Reinforcement Sensitivity Theory (r-RST). Comput. Hum. Behav. 72 (2017)