A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.
Kuan-Yu ChenChi-Sheng YangYu-Hsiu SunChien-Wei TsengMorteza FayaziXin HeSiying FengYufan YueTrevor N. MudgeRonald G. DreslinskiHun-Seok KimDavid T. BlaauwPublished in: VLSI Technology and Circuits (2022)
Keyphrases
- wireless communication
- linear algebra
- array processor
- wireless networks
- computer simulation
- wireless sensor networks
- communication networks
- computer architecture
- scan line
- semantic network
- singular value decomposition
- image processing
- domain specific
- multiresolution
- massively parallel
- feature space
- machine learning
- denoising
- radon transform
- image segmentation