Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
Sung KimMorteza FayaziAlhad DaftardarKuan-Yu ChenJielun TanSubhankar PalTutu AjayiYan XiongTrevor N. MudgeChaitali ChakrabartiDavid T. BlaauwRonald G. DreslinskiHun-Seok KimPublished in: VLSI Circuits (2021)
Keyphrases
- memory hierarchy
- control flow
- systolic array
- data flow
- scheduling algorithm
- dynamic reconfiguration
- response time
- computer architecture
- computing power
- parallel computing
- main memory
- secondary storage
- software testing
- object oriented
- data storage
- parallel architectures
- low cost
- hardware implementation
- parallel processing
- distributed memory
- distributed systems