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Jielun Tan
Publication Activity (10 Years)
Years Active: 2019-2022
Publications (10 Years): 10
Top Topics
Instruction Set Architecture
Matrix Multiplication
Memory Hierarchy
Computer Architecture
Top Venues
VLSI Circuits
IEEE J. Solid State Circuits
CoRR
WCAE
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Publications
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Javad Bagherzadeh
,
Aporva Amarnath
,
Jielun Tan
,
Subhankar Pal
,
Ronald G. Dreslinski
A Holistic Solution for Reliability of 3D Parallel Systems.
ACM J. Emerg. Technol. Comput. Syst.
18 (1) (2022)
Sung Kim
,
Morteza Fayazi
,
Alhad Daftardar
,
Kuan-Yu Chen
,
Jielun Tan
,
Subhankar Pal
,
Tutu Ajayi
,
Yan Xiong
,
Trevor N. Mudge
,
Chaitali Chakrabarti
,
David T. Blaauw
,
Ronald G. Dreslinski
,
Hun-Seok Kim
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits
57 (4) (2022)
Sung Kim
,
Morteza Fayazi
,
Alhad Daftardar
,
Kuan-Yu Chen
,
Jielun Tan
,
Subhankar Pal
,
Tutu Ajayi
,
Yan Xiong
,
Trevor N. Mudge
,
Chaitali Chakrabarti
,
David T. Blaauw
,
Ronald G. Dreslinski
,
Hun-Seok Kim
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
CoRR
(2021)
Stephen A. Zekany
,
Jielun Tan
,
James A. Connelly
,
Ronald G. Dreslinski
RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA.
SIGCSE
(2021)
Sung Kim
,
Morteza Fayazi
,
Alhad Daftardar
,
Kuan-Yu Chen
,
Jielun Tan
,
Subhankar Pal
,
Tutu Ajayi
,
Yan Xiong
,
Trevor N. Mudge
,
Chaitali Chakrabarti
,
David T. Blaauw
,
Ronald G. Dreslinski
,
Hun-Seok Kim
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
VLSI Circuits
(2021)
Stephen A. Zekany
,
Jielun Tan
,
James A. Connolly
Teaching Out-of-Order Processor Design with the RISC-V ISA.
WCAE
(2021)
Javad Bagherzadeh
,
Aporva Amarnath
,
Jielun Tan
,
Subhankar Pal
,
Ronald G. Dreslinski
R2D3: A Reliability Engine for 3D Parallel Systems.
DAC
(2020)
Dong-Hyeon Park
,
Subhankar Pal
,
Siying Feng
,
Paul Gao
,
Jielun Tan
,
Austin Rovinski
,
Shaolin Xie
,
Chun Zhao
,
Aporva Amarnath
,
Timothy Wesley
,
Jonathan Beaumont
,
Kuan-Yu Chen
,
Chaitali Chakrabarti
,
Michael Bedford Taylor
,
Trevor N. Mudge
,
David T. Blaauw
,
Hun-Seok Kim
,
Ronald G. Dreslinski
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits
55 (4) (2020)
Aporva Amarnath
,
Javad Bagherzadeh
,
Jielun Tan
,
Ronald G. Dreslinski
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology.
ISLPED
(2019)
Subhankar Pal
,
Dong-Hyeon Park
,
Siying Feng
,
Paul Gao
,
Jielun Tan
,
Austin Rovinski
,
Shaolin Xie
,
Chun Zhao
,
Aporva Amarnath
,
Timothy Wesley
,
Jonathan Beaumont
,
Kuan-Yu Chen
,
Chaitali Chakrabarti
,
Michael B. Taylor
,
Trevor N. Mudge
,
David T. Blaauw
,
Hun-Seok Kim
,
Ronald G. Dreslinski
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
VLSI Circuits
(2019)