A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Subhankar PalDong-Hyeon ParkSiying FengPaul GaoJielun TanAustin RovinskiShaolin XieChun ZhaoAporva AmarnathTimothy WesleyJonathan BeaumontKuan-Yu ChenChaitali ChakrabartiMichael B. TaylorTrevor N. MudgeDavid T. BlaauwHun-Seok KimRonald G. DreslinskiPublished in: VLSI Circuits (2019)