A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
Dong-Hyeon ParkSubhankar PalSiying FengPaul GaoJielun TanAustin RovinskiShaolin XieChun ZhaoAporva AmarnathTimothy WesleyJonathan BeaumontKuan-Yu ChenChaitali ChakrabartiMichael Bedford TaylorTrevor N. MudgeDavid T. BlaauwHun-Seok KimRonald G. DreslinskiPublished in: IEEE J. Solid State Circuits (2020)