Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture.
Yan XiongJian ZhouSubhankar PalDavid T. BlaauwH. S. KimTrevor N. MudgeRonald G. DreslinskiChaitali ChakrabartiPublished in: ISCAS (2020)
Keyphrases
- low power
- reconfigurable architecture
- neural network
- power consumption
- low cost
- high speed
- high power
- systolic array
- single chip
- wireless transmission
- vlsi circuits
- digital signal processing
- pattern recognition
- gate array
- vlsi architecture
- logic circuits
- mixed signal
- power dissipation
- power saving
- graphical models
- wireless sensor networks
- real time