Chetan Vudadha

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 15

Top Topics

Functional Decomposition

Design Methodologies

Top Venues

Microelectron. J.

Publications

Vikas Shivakumar, Chetan Vudadha
Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation. J. Circuits Syst. Comput. 33 (2) (2024)
Chetan Vudadha
Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation. ISCAS (2024)
Sharvani Gadgil, Goli Naga Sandesh, Chetan Vudadha
Design of a Ternary Logic Processor Using CNTFET Technology. Circuits Syst. Signal Process. 43 (9) (2024)
Sharvani Gadgil, Goli Naga Sandesh, Chetan Vudadha
Power efficient designs of CNTFET-based ternary SRAM. Microelectron. J. 139 (2023)
P. Sai Phaneendra, Chetan Vudadha, M. B. Srinivas
Optimization of Reversible Circuits Using Gate Pair Classification. SN Comput. Sci. 3 (1) (2022)
Siddharth T, Sharvani Gadgil, Chetan Vudadha
Design of CNTFET-based Ternary Logic circuits using Low power Encoder. iSES (2022)
Harita Sirugudi, Sharvani Gadgil, Chetan Vudadha
A Novel Low Power Ternary Multiplier Design using CNFETs. VLSI Design (2020)
P. Veda Bhanu, Chetan Vudadha, Soumya J.
FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design. ISCAS (2020)
Poojan Patel, Nikita Doddapaneni, Sharvani Gadgil, Chetan Vudadha
Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs. iSES (2019)
Chetan Vudadha, Ajay Surya, Saurabh Agrawal, M. B. Srinivas
Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Chetan Vudadha, M. B. Srinivas
Design Methodologies for Ternary Logic Circuits. ISMVL (2018)
Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas
Energy efficient design of CNFET-based multi-digit ternary adders. Microelectron. J. 75 (2018)
Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas
An ESOP Based Cube Decomposition Technique for Reversible Circuits. RC (2017)
Sai Phaneendra Parlapalli, Chetan Vudadha, M. B. Srinivas
Optimizing the Reversible Circuits Using Complementary Control Line Transformation. RC (2017)
Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. iNIS (2016)
P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas
An Optimized Design of Reversible Quantum Comparator. VLSI Design (2014)
Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED (2014)
Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI (2012)
Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI (2012)
Chetan Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas
CNFET based ternary magnitude comparator. ISCIT (2012)
Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design (2012)
P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT (2011)