A Novel Low Power Ternary Multiplier Design using CNFETs.

Harita Sirugudi Sharvani Gadgil Chetan Vudadha

Published in: VLSI Design (2020)

Keyphrases

low power
single chip
power consumption
low cost
high speed
logic circuits
vlsi architecture
low power consumption
power dissipation
cmos technology
power reduction
digital signal processing
high power
gate array
mixed signal