Syed Ershad Ahmed

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 22

Top Topics

Error Correcting

Energy Efficient

Error Resilient

Image Processing

Top Venues

J. Circuits Syst. Comput.

IEEE Embed. Syst. Lett.

Publications

Rishi Agrawal, Narayanabhatla Savyasachi Abhijith, Uppugunduru Anil Kumar, Sreehari Veeramachaneni, Syed Ershad Ahmed
Energy-Efficient Ternary Multiplier. AICAS (2024)
Aalelai Vendhan, Syed Ershad Ahmed, S. Gurunarayanan
Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders. Circuits Syst. Signal Process. 43 (7) (2024)
Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Avinash Bhat Pattaje, Suresh Nambi, Syed Ershad Ahmed
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications. IEEE Embed. Syst. Lett. 15 (3) (2023)
Pramod Alamuri, Uppugunduru Anil Kumar, Vallepu Vannuru, Syed Ershad Ahmed
Improved approximate multiplier architecture for image processing and neural network applications. Microprocess. Microsystems 101 (2023)
Sangireddy Tharuni, Basani Harshavardhan Reddy, Bhukya Mamatha, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni
Power Efficient Approximate Ternary Subtractor for Image Processing Applications. iSES (2023)
Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni, Syed Ershad Ahmed
Design of Energy Efficient Posit Multiplier. ACM Great Lakes Symposium on VLSI (2023)
Sahith Guturu, Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Syed Ershad Ahmed
Design methodology for highly accurate approximate multipliers for error resilient applications. Comput. Electr. Eng. 110 (2023)
Aroondhati Bhure, P. Smriti, Vinay Dhanote, Uppugunduru Anil Kumar, Syed Ershad Ahmed
A General Methodology to Optimize Flagged Constant Addition. J. Circuits Syst. Comput. 32 (2) (2023)
Anil Kumar Uppugunduru, S. Vignesh Bharadwaj, Syed Ershad Ahmed
Compressor based hybrid approximate multiplier architectures with efficient error correction logic. Comput. Electr. Eng. 104 (Part) (2022)
Uppugunduru Anil Kumar, G. Sahith, Sumit K. Chatterjee, Syed Ershad Ahmed
A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications. J. Circuits Syst. Comput. 31 (3) (2022)
Uppugunduru Anil Kumar, Sumit K. Chatterjee, Syed Ershad Ahmed
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module. IEEE Embed. Syst. Lett. 14 (2) (2022)
Uppugunduru Anil Kumar, Sahith Guturu, Syed Ershad Ahmed
Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation. Microprocess. Microsystems 94 (2022)
Uppugunduru Anil Kumar, Goli Naga Sandesh, Dhoti Ojusteja, Syed Ershad Ahmed
Lower part OR based Approximate Multiplier for Error Resilient Applications. iSES (2021)
Syed Ershad Ahmed, Yerasuri Mohana Sri Krishna
An Efficient Hardware Approach for Approximate Logarithmic Computation. J. Circuits Syst. Comput. 30 (9) (2021)
Suresh Nambi, Uppugunduru Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, Syed Ershad Ahmed
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications. IEEE Embed. Syst. Lett. 13 (4) (2021)
Uppugunduru Anil Kumar, Ratna Kumari Chintakunta, Sandeep Kumar, K. Jamal, Syed Ershad Ahmed
Approximate Multiplier Architectures for Error Resilient Applications. iSES (2021)
Sahith Guturu, Anil Kumar Uppugunduru, Sridhar Thota, Syed Ershad Ahmed
Power-Efficient MLOA for error resilient applications. iSES (2021)
Uppugunduru Anil Kumar, Nishant Jain, Sumit K. Chatterjee, Syed Ershad Ahmed
Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing. MIND (2) (2020)
Syed Ershad Ahmed, M. B. Srinivas
An Improved Logarithmic Multiplier for Media Processing. J. Signal Process. Syst. 91 (6) (2019)
Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas
Improved designs of digit-by-digit decimal multiplier. Integr. 61 (2018)
Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas
A Hybrid Energy Efficient Digital Comparator. VLSI Design (2016)
Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas
An Iterative Logarithmic Multiplier with Improved Precision. ARITH (2016)
Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. VLSI Design (2014)
Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed, M. B. Srinivas
A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits. APCCAS (2014)
Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI (2012)
Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI (2012)
Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design (2012)
Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Modified Twin Precision Multiplier with 2D Bypassing Technique. ISED (2012)
Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Prefix Based Reconfigurable Adder. ISVLSI (2011)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD (2011)
P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT (2011)
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED (2011)