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Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
Mahesh Kumar Adimulam
Krishna Kumar Movva
Sreehari Veeramachaneni
N. Moorthy Muthukrishnan
Mandalika B. Srinivas
Published in:
APCCAS (2010)
Keyphrases
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low power
analog to digital converter
mixed signal
variable resolution
power consumption
low cost
high speed
vlsi architecture
image sensor
multi channel
multiresolution
single chip
cmos technology
digital signal processing
data flow
cmos image sensor
state space
moving objects
low power consumption