Saurabh Kotiyal

Publication Activity (10 Years)

Years Active: 2005-2016
Publications (10 Years): 1

Top Topics

Design Methodologies

Top Venues

Microelectron. J.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Saurabh Kotiyal, Himanshu Thapliyal
Design Methodologies for Reversible Logic Based Barrel Shifters. J. Circuits Syst. Comput. 25 (2) (2016)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Reversible logic based multiplication computing unit using binary tree data structure. J. Supercomput. 71 (7) (2015)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. VLSI Design (2014)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. Trans. Comput. Sci. 24 (2014)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Efficient reversible NOR gates and their mapping in optical computing domain. Microelectron. J. 45 (6) (2014)
Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
Design of Testable Reversible Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. ISVLSI (2012)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE (2012)
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. VLSI Design (2006)
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format CoRR (2006)
Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. CSC (2005)