Nagarajan Ranganathan

Publication Activity (10 Years)

Years Active: 1990-2018
Publications (10 Years): 8

Top Topics

Insider Attacks

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Santosh Aditham, Nagarajan Ranganathan
A System Architecture for the Detection of Insider Attacks in Big Data Systems. IEEE Trans. Dependable Secur. Comput. 15 (6) (2018)
Himanshu Thapliyal, Nagarajan Ranganathan
Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits. CoRR (2017)
Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori
LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems. IPDPS Workshops (2017)
Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M. Chiarulli, Steven P. Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan, Vijaykrishnan Narayanan
Enabling New Computation Paradigms with HyperFET - An Emerging Device. IEEE Trans. Multi Scale Comput. Syst. 2 (1) (2016)
Santosh Aditham, Nagarajan Ranganathan
A System Architecture for the Detection of Insider Attacks in Big Data Systems. CoRR (2016)
Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori
Memory access pattern based insider threat detection in big data systems. IEEE BigData (2016)
Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori
Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms. CoRR (2016)
Santosh Aditham, Nagarajan Ranganathan
A Novel Control-flow based Intrusion Detection Technique for Big Data Systems. CoRR (2016)
Santosh Aditham, Nagarajan Ranganathan
An energy-aware scheduling heuristic for distributed systems using non-cooperative games. IGSC (2015)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Reversible logic based multiplication computing unit using binary tree data structure. J. Supercomput. 71 (7) (2015)
Santosh Aditham, Nagarajan Ranganathan
A novel framework for mitigating insider attacks in big data systems. IEEE BigData (2015)
Matthew A. Morrison, Nagarajan Ranganathan, Jay Ligatti
Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Tony Casagrande, Nagarajan Ranganathan
GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. DATE (2015)
Yue Wang, Nagarajan Ranganathan
A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures. ISVLSI (2014)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. VLSI Design (2014)
Matthew Morrison, Nagarajan Ranganathan
Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (7) (2014)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. Trans. Comput. Sci. 24 (2014)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Efficient reversible NOR gates and their mapping in optical computing domain. Microelectron. J. 45 (6) (2014)
Matthew Morrison, Nagarajan Ranganathan
Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. VLSI Design (2014)
Sandip Kundu, Saraju P. Mohanty, Nagarajan Ranganathan
Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. IET Circuits Devices Syst. 7 (5) (2013)
Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Matthew Morrison, Nagarajan Ranganathan
A novel optimization method for reversible logic circuit minimization. ISVLSI (2013)
Himanshu Thapliyal, Apeksha Bhatt, Nagarajan Ranganathan
A new CRL gate as super class of Fredkin gate to design reversible quantum circuits. MWSCAS (2013)
Matthew Lewandowski, Nagarajan Ranganathan, Matthew Morrison
Behavioral model of integrated qubit gates for quantum reversible logic design. ISVLSI (2013)
Himanshu Thapliyal, Nagarajan Ranganathan
Design of efficient reversible logic-based binary and BCD adder circuits. ACM J. Emerg. Technol. Comput. Syst. 9 (3) (2013)
Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal
Design of Testable Reversible Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan
Run-time power-gating in caches of GPUs for leakage energy savings. DATE (2012)
Himanshu Thapliyal, Nagarajan Ranganathan
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. VLSI Design (2012)
Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.
Dynamic clock stretching for variation compensation in VLSI circuit design. ACM J. Emerg. Technol. Comput. Syst. 8 (3) (2012)
Matthew Morrison, Nagarajan Ranganathan
Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. ISVLSI (2012)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. ISVLSI (2012)
Himanshu Thapliyal, Nagarajan Ranganathan
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. ISVLSI (2012)
Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan
Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE (2012)
Matthew Morrison, Matthew Lewandowski, Nagarajan Ranganathan
Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. ISVLSI (2012)
Upavan Gupta, Nagarajan Ranganathan
A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. IEEE Trans. Very Large Scale Integr. Syst. 19 (9) (2011)
Matthew Morrison, Nagarajan Ranganathan
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. ISVLSI (2011)
Himanshu Thapliyal, Nagarajan Ranganathan
Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits CoRR (2011)
Ransford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan
Redundancy Mining for Soft Error Detection in Multicore Processors. IEEE Trans. Computers 60 (8) (2011)
Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. IEEE Trans. Computers 60 (11) (2011)
Himanshu Thapliyal, Nagarajan Ranganathan
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. VLSI Design (2010)
Himanshu Thapliyal, Nagarajan Ranganathan
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. 6 (4) (2010)
Upavan Gupta, Nagarajan Ranganathan
A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. IEEE Trans. Knowl. Data Eng. 22 (4) (2010)
Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam
Variation-aware multimetric optimization during gate sizing. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Himanshu Thapliyal, Nagarajan Ranganathan
Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. ISCAS (2009)
Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
A Framework for Power-Gating Functional Units in Embedded Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 17 (11) (2009)
Koustav Bhattacharya, Nagarajan Ranganathan
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design (2009)
Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan
A VLSI System Architecture for Optical Flow Computation. ISCAS (2009)
Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
Exploring Compiler Optimizations for Enhancing Power Gating. ISCAS (2009)
Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Himanshu Thapliyal, Nagarajan Ranganathan
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design (2009)
Himanshu Thapliyal, Nagarajan Ranganathan
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. ISVLSI (2009)
Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
Compiler-directed leakage reduction in embedded microprocessors. ICCD (2009)
Koustav Bhattacharya, Nagarajan Ranganathan
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. ISVLSI (2009)
Koustav Bhattacharya, Nagarajan Ranganathan
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED (2009)
Koustav Bhattacharya, Nagarajan Ranganathan
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED (2008)
Koustav Bhattacharya, Nagarajan Ranganathan
A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI (2008)
Venkataraman Mahalingam, Nagarajan Ranganathan
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI (2008)
Upavan Gupta, Nagarajan Ranganathan
A microeconomic approach to multi-objective spatial clustering. ICPR (2008)
Upavan Gupta, Nagarajan Ranganathan
An expected-utility based approach to variation aware VLSI optimization under scarce information. ISLPED (2008)
Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan
VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Comput. Digit. Tech. 1 (5) (2007)
Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan
Improving the reliability of on-chip L2 cache using redundancy. ICCD (2007)
Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. VLSI Design (2007)
Upavan Gupta, Nagarajan Ranganathan
A microeconomic approach to multi-robot team formation. IROS (2007)
Upavan Gupta, Nagarajan Ranganathan
Multievent Crisis Management Using Noncooperative Multistep Games. IEEE Trans. Computers 56 (5) (2007)
Narender Hanchate, Nagarajan Ranganathan
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI (2007)
Narender Hanchate, Nagarajan Ranganathan
Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI (2007)
K. P. Subbalakshmi, Rajarathnam Chandramouli, Nagarajan Ranganathan
A Sequential Distinguisher for Covert Channel Identification. Int. J. Netw. Secur. 5 (3) (2007)
Venkataraman Mahalingam, Nagarajan Ranganathan
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55 (12) (2006)
Saraju P. Mohanty, Nagarajan Ranganathan, Karthikeyan Balakrishnan
A dual voltage-frequency VLSI chip for image watermarking in DCT domain. IEEE Trans. Circuits Syst. II Express Briefs (5) (2006)
Aswath Oruganti, Nagarajan Ranganathan
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. VLSI Design (2006)
Narender Hanchate, Nagarajan Ranganathan
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. 11 (3) (2006)
Narender Hanchate, Nagarajan Ranganathan
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design (2006)
Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI (2006)
Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh
An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. VLSI Design (2006)
Narender Hanchate, Nagarajan Ranganathan
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers 55 (8) (2006)
Narender Hanchate, Nagarajan Ranganathan
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED (2006)
Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
DC) design. IEEE Trans. Very Large Scale Integr. Syst. 13 (7) (2005)
Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
/DC) design (Corrected)*. IEEE Trans. Very Large Scale Integr. Syst. 13 (8) (2005)
Narender Hanchate, Nagarajan Ranganathan
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design (2004)
Narender Hanchate, Nagarajan Ranganathan
LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 12 (2) (2004)
Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui
Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI (2004)
Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design (2004)
Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design (2004)
Saraju P. Mohanty, Nagarajan Ranganathan
A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 12 (6) (2004)
Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi
Transient power minimization through datapath scheduling in multiple supply voltage environment. ICECS (2003)
Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan
VBR video traffic management using a predictor-based architecture. Comput. Commun. 23 (1) (2000)
Veeraraghavan N. Ramaswamy, Kamesh Namuduri, Nagarajan Ranganathan
Context modeling of wavelet coefficients in EZW-based lossless image coding. ICASSP (1999)
Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan
An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks. ISCC (1998)
Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu
A VLSI ATM Switch Architecture for VBR Traffic. VLSI Design (1998)
Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar
A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. Circuits Syst. Video Technol. 8 (4) (1998)
Nagarajan Ranganathan, Rajesh Chandra
A linear systolic algorithm and architecture for convex bipartite matching. HiPC (1996)
Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar
DFLAP: a dynamic frequency linear array processor. ICIP (2) (1996)
Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam
A high speed systolic architecture for labeling connected components in an image. IEEE Trans. Syst. Man Cybern. 25 (3) (1995)
Nagarajan Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri
A lossless image compression algorithm using variable block size segmentation. IEEE Trans. Image Process. 4 (10) (1995)
Kameswara Rao Namuduri, Rajiv Mehrotra, Nagarajan Ranganathan
Efficient computation of gabor filter based multiresolution responses. Pattern Recognit. 27 (7) (1994)
Rajiv Mehrotra, Kameswara Rao Namuduri, Nagarajan Ranganathan
Gabor filter-based edge detection. Pattern Recognit. 25 (12) (1992)
Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam
A high speed systolic architecture for labeling connected components in an image. SPDP (1991)
Rajiv Mehrotra, Sanjay Nichani, Nagarajan Ranganathan
Corner detection. Pattern Recognit. 23 (11) (1990)