Narayanan Vijaykrishnan

Publication Activity (10 Years)

Years Active: 1996-2018
Publications (10 Years): 1

Top Venues

ISLPED

Publications

Sandeep Krishna Thirumala, Arnab Raha, Hrishikesh Jayakumar, Kaisheng Ma, Narayanan Vijaykrishnan, Vijay Raghunathan, Sumeet Kumar Gupta
Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems. ISLPED (2018)
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
A case for heterogeneous on-chip interconnects for CMPs. ISCA (2011)
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA (2011)
Feng Wang, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan
Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. 71 (5) (2011)
Jawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
applications. ASP-DAC (2010)
Aditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan
A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching. DATE (2010)
Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan
Investigating the impact of NBTI on different power saving cache strategies. DATE (2010)
Vikram Sampath Kumar, Kevin M. Irick, Ahmed Al-Maashri, Narayanan Vijaykrishnan
A Scalable Bandwidth Aware Architecture for Connected Component Labeling. ISVLSI (2010)
Sungmin Bae, Narayanan Vijaykrishnan
Thermal Gradient Aware Clock Skew Scheduling for FPGAs. FPL (2010)
Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Total Power Optimization for Combinational Logic Using Genetic Algorithms. J. Signal Process. Syst. 58 (2) (2010)
Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
Compiler-assisted soft error detection under performance and energy constraints in embedded systems. ACM Trans. Embed. Comput. Syst. 8 (4) (2009)
Sungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan
A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications. ISVLSI (2009)
Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir
and Grid Topologies. Int. J. Distributed Sens. Networks 5 (3) (2009)
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud
Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect. IET Circuits Devices Syst. 3 (2) (2009)
Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
A case for dynamic frequency tuning in on-chip networks. MICRO (2009)
Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan
: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. Int. J. Parallel Program. 37 (4) (2009)
Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan
Exploiting clock skew scheduling for FPGA. DATE (2009)
Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA (2009)
Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan
A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC (2009)
Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam
Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures. ISLPED (2008)
Suresh Srinivasan, Lin Li, Martino Ruggiero, Federico Angiolini, Narayanan Vijaykrishnan, Luca Benini
Exploring architectural solutions for energy optimisations in bus-based system-on-chip. IET Comput. Digit. Tech. 2 (5) (2008)
Soumya Eachempati, Vinay Saripalli, Narayanan Vijaykrishnan, Suman Datta
Reconfigurable BDD based quantum circuits. NANOARCH (2008)
Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA (2008)
Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
Design Space Exploration for 3-D Cache. IEEE Trans. Very Large Scale Integr. Syst. 16 (4) (2008)
Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie
Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD (2008)
Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman
Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie
Case Study of Reliability-Aware and Low-Power Design. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu
Hierarchical Soft Error Estimation Tool (HSEET). ISQED (2008)
Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
Analysis and solutions to issue queue process variation. DSN (2008)
Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir
On the Detection of Clones in Sensor Networks Using Random Key Predistribution. IEEE Trans. Syst. Man Cybern. Part C 37 (6) (2007)
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. ISQED (2007)
Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin
Impact of NBTI on FPGAs. VLSI Design (2007)
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA (2007)
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan
FPGA routing architecture analysis under variations. ICCD (2007)
Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin
Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI (2007)
Aman Gayasen, Suresh Srinivasan, Narayanan Vijaykrishnan, Mahmut T. Kandemir
Design of power-aware FPGA fabrics. Int. J. Embed. Syst. 3 (1/2) (2007)
Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
Optimising power efficiency in trace cache fetch unit. IET Comput. Digit. Tech. 1 (4) (2007)
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
Thermally robust clocking schemes for 3D integrated circuits. DATE (2007)
Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio
OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. IEEE Trans. Computers 56 (1) (2007)
Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Hot Interconnects (2007)
Greg M. Link, Narayanan Vijaykrishnan
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip CoRR (2007)
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud
Assessing carbon nanotube bundle interconnect for future FPGA architectures. DATE (2007)
Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan
Variation-aware task allocation and scheduling for MPSoC. ICCAD (2007)
Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
Reliability-aware Co-synthesis for Embedded Systems. J. VLSI Signal Process. 49 (1) (2007)
Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
Variation Impact on SER of Combinational Circuits. ISQED (2007)
Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
Architecting Microprocessor Components in 3D Design Space. VLSI Design (2007)
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. ISVLSI (2007)
Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Thermal-Aware Task Allocation and Scheduling for Embedded Systems CoRR (2007)
Madhu Mutyam, Narayanan Vijaykrishnan
Working with process variation aware caches. DATE (2007)
Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
On-chip bus thermal analysis and optimisation. IET Comput. Digit. Tech. 1 (5) (2007)
Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
Variation Analysis of CAM Cells. ISQED (2007)
Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin
Reducing non-deterministic loads in low-power caches via early cache set resolution. Microprocess. Microsystems 31 (5) (2007)
Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie
Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI (2006)
Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das
Exploring Fault-Tolerant Network-on-Chip Architectures. DSN (2006)
Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin
A Parallel Architecture for Hardware Face Detection. ISVLSI (2006)
Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo
Leakage Optimized DECAP Design for FPGAs. APCCAS (2006)
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari
FLAW: FPGA lifetime awareness. DAC (2006)
Suresh Srinivasan, Narayanan Vijaykrishnan
Variation Aware Placement for FPGAs. ISVLSI (2006)
Matthew Pirretti, Sencun Zhu, Narayanan Vijaykrishnan, Patrick D. McDaniel, Mahmut T. Kandemir, Richard R. Brooks
The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. Int. J. Distributed Sens. Networks 2 (3) (2006)
Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design (2006)
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA (2006)
Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Compiler-directed thermal management for VLIW functional units. LCTES (2006)
Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
Object duplication for improving reliability. ASP-DAC (2006)
Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. IEEE Trans. Circuits Syst. Video Technol. 16 (5) (2006)
Wei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embed. Comput. Syst. 5 (1) (2006)
Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
On-chip bus thermal analysis and optimization. DATE (2006)
G. Chen, Liping Xue, Jungsub Kim, Kanwaldeep Sobti, Lanping Deng, Xiaobai Sun, Nikos Pitsianis, Chaitali Chakrabarti, Mahmut T. Kandemir, Narayanan Vijaykrishnan
Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations. SoCC (2006)
Narayanan Vijaykrishnan, Yuan Xie
Reliability Concerns in Embedded System Designs. Computer 39 (1) (2006)
Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman
Switch Box Architectures for Three-Dimensional FPGAs. FCCM (2006)
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED (2006)
Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
Thermal characterization and optimization in platform FPGAs. ICCAD (2006)
Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne H. Wolf
An efficient architecture for motion estimation and compensation in the transform domain. IEEE Trans. Circuits Syst. Video Technol. 16 (2) (2006)
Priya Sundararajan, Sridhar Krishnamurthy, Narayanan Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman
Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs. SoCC (2006)
Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin
Priority scheduling in digital microfluidics-based biochips. DATE (2006)
Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI (2006)
Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects. Nano-Net (2006)
R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design (2006)
Greg M. Link, Narayanan Vijaykrishnan
Thermal Trends in Emerging Technologies. ISQED (2006)
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED (2006)
Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. MICRO (2006)
Suresh Srinivasan, Raghavan Ramadoss, Narayanan Vijaykrishnan
Process Variation Aware Parallelization Strategies for MPSoCs. SoCC (2006)
Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli
Block-based frequency scalable technique for efficient hierarchical coding. IEEE Trans. Signal Process. 54 (7) (2006)
Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
Designing reliable circuit in the presence of soft errors. ASP-DAC (2005)
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD (2005)
Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. IEEE Trans. Computers 54 (6) (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design (2005)
Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
Leakage-Aware Interconnect for On-Chip Network. DATE (2005)
Narayanan Vijaykrishnan
Soft errors: is the concern for soft-errors overblown? ITC (2005)
Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
Compiler-Directed Instruction Duplication for Soft Error Detection. DATE (2005)
Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo
Improving Java performance using dynamic method migration on FPGAs. Int. J. Embed. Syst. 1 (3/4) (2005)
Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Soft errors issues in low-power caches. IEEE Trans. Very Large Scale Integr. Syst. 13 (10) (2005)
Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin
Implementing LDPC Decoding on Network-on-Chip. VLSI Design (2005)
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. DATE (2005)
Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE (2005)
Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE (2005)
Greg M. Link, Narayanan Vijaykrishnan
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. DATE (2005)
Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Chita R. Das
Design and analysis of an NoC architecture from performance, reliability and energy perspective. ANCS (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Narayanan Vijaykrishnan