Madhu Mutyam

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 24

Top Topics

Cache Management

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Abdun Nihaal, Madhu Mutyam
Selective Memory Compression for GPU Memory Oversubscription Management. ICPP (2024)
Praseetha M, Madhu Mutyam, Venkata Kalyan Tavva
Cache Line Pinning for Mitigating Row Hammer Attack. ICPP (2024)
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Joe Augustine, Kanakagiri Raghavendra, John Jose, Madhu Mutyam
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. ICCD (2020)
Praveen Alapati, Venkata Kalyan Tavva, Madhu Mutyam
A Scalable and Energy-Efficient Concurrent Binary Search Tree With Fatnodes. IEEE Trans. Sustain. Comput. 5 (4) (2020)
S. R. Swamy Saranam Chongala, Sumitha George, Hariram Thirucherai Govindarajan, Jagadish Kotra, Madhu Mutyam, John Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (11) (2020)
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
Fuzzy fairness controller for NVMe SSDs. ICS (2020)
Praveen Alapati, Madhu Mutyam, Swamy Saranam
Concurrent Treaps and Impact of Locking Objects. New Gener. Comput. 38 (1) (2020)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
Formal Modeling and Verification of a Victim DRAM Cache. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Puneet Saraf, Madhu Mutyam
Endurance enhancement of write-optimized STT-RAM caches. MEMSYS (2019)
Sayantan Ray, Madhu Mutyam
POSTER: Variable Sized Cache-Block Compaction. PACT (2019)
Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam
Post-Model Validation of Victim DRAM Caches. ICCD (2019)
S. R. Swamy Saranam, Madhu Mutyam
TDC: Tagless DRAM Cache. ISVLSI (2018)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. IEEE Comput. Archit. Lett. 17 (2) (2018)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan
CAMO: A novel cache management organization for GPGPUs. ASP-DAC (2018)
Dennis Antony Varkey, Biswabandan Panda, Madhu Mutyam
RCTP: Region Correlated Temporal Prefetcher. ICCD (2017)
Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. VLSI Design (2017)
Praveen Alapati, Venkata Kalyan Tavva, Madhu Mutyam
FatCBST: Concurrent Binary Search Tree with Fatnodes. HPCC/SmartCity/DSS (2017)
Praveen Alapati, Swamy Saranam, Madhu Mutyam
Concurrent Treaps. ICA3PP (2017)
Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam
MBZip: Multiblock Data Compression. ACM Trans. Archit. Code Optim. 14 (4) (2017)
Gnaneswara Rao Jonna, Vamana Murthi Thuniki, Madhu Mutyam
CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router. ARCS (2016)
Kanakagiri Raghavendra, Biswabandan Panda, Madhu Mutyam
PBC: Prefetched Blocks Compaction. IEEE Trans. Computers 65 (8) (2016)
Tripti S. Warrier, Kanakagiri Raghavendra, Madhu Mutyam
SkipCache: application aware cache management for chip multi-processors. IET Comput. Digit. Tech. 9 (6) (2015)
Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam
SAMO: store aware memory optimizations. Conf. Computing Frontiers (2014)
Pritam Majumder, T. Venkata Kalyan, Madhu Mutyam
SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache. ICCD (2014)
Prasanna Venkatesh Rengasamy, Madhu Mutyam
Using packet information for efficient communication in NoCs. NOCS (2014)
T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam
Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time. ASP-DAC (2014)
Sudharsan Jagathrakshakan, Venkata Kalyan Tavva, Madhu Mutyam
Data remapping for an energy efficient burst chop in DRAM memory systems. PACT (2014)
John Jose, Madhu Mutyam
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs. ACM Trans. Design Autom. Electr. Syst. 19 (4) (2014)
Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam
Minimally buffered single-cycle deflection router. DATE (2014)
Venkata Kalyan Tawa, Ravi Kasha, Madhu Mutyam
EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices. ACM Trans. Archit. Code Optim. 11 (3) (2014)
Tripti S. Warrier, B. Anupama, Madhu Mutyam
An Application-Aware Cache Replacement Policy for Last-Level Caches. ARCS (2013)
John Jose, Bhawna Nayak, Damarla Kranthi Kumar, Madhu Mutyam
DeBAR: deflection based adaptive router with minimal buffering. DATE (2013)
Bhawna Nayak, John Jose, Madhu Mutyam
SLIDER: Smart Late Injection DEflection Router for mesh NoCs. ICCD (2013)
Arpit Joshi, Prasanna Venkatesh Rengasamy, Madhu Mutyam
Prevention slot flow-control mechanism for low latency torus network-on-chip. IET Comput. Digit. Tech. 7 (6) (2013)
Madhu Mutyam
Fibonacci Codes for Crosstalk Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Kanakagiri Raghavendra, Tripti S. Warrier, Madhu Mutyam
SkipCache: miss-rate aware cache management. PACT (2012)
C. J. Janraj, T. Venkata Kalyan, Tripti S. Warrier, Madhu Mutyam
Way Sharing Set Associative Cache Architecture. VLSI Design (2012)
John Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam
TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. ICCAD (2012)
Kartikey Mittal, Arpit Joshi, Madhu Mutyam
Timing variation-aware scheduling and resource binding in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 16 (4) (2011)
John Jose, J. Shiva Shankar, K. V. Mahathi, Damarla Kranthi Kumar, Madhu Mutyam
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs. NoCArc@MICRO (2011)
Arpit Joshi, Madhu Mutyam
Prevention flow-control for low latency torus networks-on-chip. NOCS (2011)
Madhu Mutyam
Selective shielding technique to eliminate crosstalk transitions. ACM Trans. Design Autom. Electr. Syst. 14 (3) (2009)
Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin
Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers 58 (7) (2009)
Nallamothu Satyanarayana, A. Vinaya Babu, Madhu Mutyam
Delay-efficient bus encoding techniques. Microprocess. Microsystems 33 (5-6) (2009)
Kanakagiri Raghavendra, Madhu Mutyam
Process Variation Aware Issue Queue Design. DATE (2008)
T. Venkata Kalyan, Madhu Mutyam
Word-interleaved cache: an energy efficient data cache architecture. ISLPED (2008)
T. Venkata Kalyan, Madhu Mutyam, P. Vijaya Sankara Rao
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. VLSI Design (2008)
Mohammed Abid Hussain, Madhu Mutyam
Block remap with turnoff: A variation-tolerant cache design technique. ASP-DAC (2008)
Abu Saad Papa, Madhu Mutyam
Power management of variation aware chip multiprocessors. ACM Great Lakes Symposium on VLSI (2008)
Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin
Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI (2007)
Madhu Mutyam
Selective shielding: a crosstalk-free bus encoding technique. ICCAD (2007)
Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu
Exploiting on-chip data behavior for delay minimization. SLIP (2007)
Madhu Mutyam, Narayanan Vijaykrishnan
Working with process variation aware caches. DATE (2007)
Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
Variation Analysis of CAM Cells. ISQED (2007)
K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI (2006)
Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Compiler-directed thermal management for VLIW functional units. LCTES (2006)
Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI (2006)
K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electron. 2 (3) (2006)
Madhu Mutyam
Rewriting P systems: improved hierarchies. Theor. Comput. Sci. 334 (1-3) (2005)
Madhu Mutyam, Kamala Krithivasan, A. Siddhartha Reddy
On Characterizing Recursively Enumerable Languages by Insertion Grammars. Fundam. Informaticae 64 (1-4) (2005)
Madhu Mutyam, Kamala Krithivasan
Length Synchronization Context-Free Grammars. J. Autom. Lang. Comb. 9 (4) (2004)
Madhu Mutyam
Preventing Crosstalk Delay using Fibonacci Representation. VLSI Design (2004)
Madhu Mutyam
Descriptional Complexity of Rewriting P Systems. J. Autom. Lang. Comb. 9 (2/3) (2004)
P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam
A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design (2004)
Madhu Mutyam, Vaka Jaya Prakash, Kamala Krithivasan
Rewriting Tissue P Systems. J. Univers. Comput. Sci. 10 (9) (2004)
Madhu Mutyam, Kamala Krithivasan
On a class of P automata. Int. J. Comput. Math. 80 (9) (2003)
Madhu Mutyam
Probabilistic Rewriting P Systems. Int. J. Found. Comput. Sci. 14 (1) (2003)
M. Sakthi Balan, Kamala Krithivasan, Madhu Mutyam
Some Variants in Communication of Parallel Communicating Pushdown Automata. J. Autom. Lang. Comb. 8 (3) (2003)
Rodica Ceterchi, Madhu Mutyam, Gheorghe Paun, K. G. Subramanian
Array-rewriting P systems. Nat. Comput. 2 (3) (2003)
Madhu Mutyam, Kamala Krithivasan
A Survey of Some Variants of P Systems. WMC-CdeA (2002)
Madhu Mutyam, Kamala Krithivasan
Improved Results about Universality of P systems. Bull. EATCS 76 (2002)
Madhu Mutyam, Kamala Krithivasan
Generalized normal form for rewriting P systems. Acta Informatica 38 (10) (2002)
Madhu Mutyam
Complexity Issues in Rewriting P Systems. DCFS (2002)
Madhu Mutyam, Kamala Krithivasan
A Note on Hybrid P Systems. Grammars 5 (3) (2002)
Kamala Krithivasan, Madhu Mutyam
Contextual P Systems. Fundam. Informaticae 49 (1-3) (2002)
Madhu Mutyam, Kamala Krithivasan
P Systems with Membrane Creation: Universality and Efficiency. MCU (2001)
Madhu Mutyam, Kamala Krithivasan
Universality Results for Some Variants of P Systems. WMP (2000)