S. Ramesh

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 5

Top Topics

Linear Temporal Logic

Verification Method

Top Venues

Formal Aspects Comput.

Softw. Test. Verification Reliab.

J. Syst. Softw.

Publications

Dnyanesh Rajpathak, Prakash Mohan Peranandam, S. Ramesh
Automatic development of requirement linking matrix based on semantic similarity for robust software development. J. Syst. Softw. 186 (2022)
Sofia Ananieva, Sandra Greiner, Timo Kehrer, Jacob Krüger, Thomas Kühn, Lukas Linsbauer, Sten Grüner, Anne Koziolek, Henrik Lönn, S. Ramesh, Ralf H. Reussner
A conceptual model for unifying variability in space and time: Rationale, validation, and illustrative applications. Empir. Softw. Eng. 27 (5) (2022)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
Formal Modeling and Verification of a Victim DRAM Cache. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Ganesh Khandu Narwane, José Angel Galindo, Shankara Narayanan Krishna, David Benavides, Jean-Vivien Millo, S. Ramesh
Traceability Analyses between Features and Assets in Software Product Lines. Entropy 18 (8) (2016)
Manoj G. Dixit, S. Ramesh, Pallab Dasgupta
Time-budgeting: a component based development methodology for real-time embedded systems. Formal Aspects Comput. 26 (3) (2014)
Swarup Mohalik, Ambar A. Gadkari, Anand Yeolekar, K. C. Shashidhar, S. Ramesh
Automatic test case generation from Simulink/Stateflow models using model checking. Softw. Test. Verification Reliab. 24 (2) (2014)
Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh
Translation Validation for Stateflow to C. DAC (2014)
Alexandre Petrenko, Arnaud Dury, S. Ramesh, Swarup Mohalik
A Method and Tool for Test Optimization for Automotive Controllers. ICST Workshops (2013)
Jean-Vivien Millo, Frédéric Mallet, Anthony Coadou, S. Ramesh
Scenario-based verification in presence of variability using a synchronous approach. Frontiers Comput. Sci. 7 (5) (2013)
Manoranjan Satpathy, Colin F. Snook, Silky Arora, S. Ramesh, Michael J. Butler
Systematic Development of Control Designs via Formal Refinement. MODELSWARD (2013)
Jean-Vivien Millo, S. Ramesh, Shankara Narayanan Krishna, Ganesh Khandu Narwane
Compositional Verification of Software Product Lines. IFM (2013)
Swarup Mohalik, Devesh B. Chokshi, Manoj G. Dixit, A. C. Rajeev, S. Ramesh
Scalable model-checking for precise end-to-end latency computation. CACSD (2013)
Manoranjan Satpathy, S. Ramesh, Colin F. Snook, Neeraj Kumar Singh, Michael J. Butler
A mixed approach to rigorous development of control designs. CACSD (2013)
A. C. Rajeev, Swarup Mohalik, S. Ramesh
Verifying timing synchronization constraints in distributed embedded architectures. DATE (2012)
Shankara Narayanan Krishna, Ganesh Khandu Narwane, S. Ramesh, Swarup Mohalik, Jean-Vivien Millo
Formalizing Traceability and Derivability in Software Product Lines CoRR (2012)
Silky Arora, Prahladavaradan Sampath, S. Ramesh
Resolving uncertainty in automotive feature interactions. RE (2012)
Manoranjan Satpathy, Anand Yeolekar, Prakash Peranandam, S. Ramesh
Efficient coverage of parallel and hierarchical stateflow models for test case generation. Softw. Test. Verification Reliab. 22 (7) (2012)
Swarup Mohalik, S. Ramesh, Jean-Vivien Millo, Shankara Narayanan Krishna, Ganesh Khandu Narwane
Tracing SPLs precisely and efficiently. SPLC (1) (2012)
Sachin Raviram, Prakash Peranandam, Manoranjan Satpathy, S. Ramesh
SmartTestGen+: A Test Suite Booster for Enhanced Structural Coverage. ICTAC (2012)
Jean-Vivien Millo, S. Ramesh, Shankara Narayanan Krishna, Ganesh Khandu Narwane
Compositional Verification of Evolving Software Product Lines CoRR (2012)
Prakash Peranandam, Sachin Raviram, Manoranjan Satpathy, Anand Yeolekar, Ambar A. Gadkari, S. Ramesh
An integrated test generation tool for enhanced coverage of Simulink/Stateflow models. DATE (2012)
Jean-Vivien Millo, S. Ramesh
Relating Requirement and Design Variabilities. APSEC Workshops (2012)
Manoj G. Dixit, S. Ramesh, Pallab Dasgupta
Some results on Parametric Temporal Logic. Inf. Process. Lett. 111 (20) (2011)
Jean-Vivien Millo, Swarup Mohalik, S. Ramesh
Integrated analysis of software product lines: a constraint based framework for consistency, liveness, and commonness checking. ISEC (2011)
Sumit Kumar Jha, Christopher James Langmead, Swarup Mohalik, S. Ramesh
When to stop verification?: Statistical trade-off between expected loss and simulation cost. DATE (2011)
Manfred Broy, Samarjit Chakraborty, Dip Goswami, S. Ramesh, Manoranjan Satpathy, Stefan Resmerita, Wolfgang Pree
Cross-layer analysis, testing and verification of automotive control software. EMSOFT (2011)
Prahladavaradan Sampath, Silky Arora, S. Ramesh
Evolving specifications formally. RE (2011)
A. C. Rajeev, Prahladavaradan Sampath, K. C. Shashidhar, S. Ramesh
CoGenTe: a tool for code generator testing. ASE (2010)
Manoj G. Dixit, Pallab Dasgupta, S. Ramesh
Taming the component timing: A CBD methodology for real-time embedded systems. DATE (2010)
A. C. Rajeev, Swarup Mohalik, Manoj G. Dixit, Devesh B. Chokshi, S. Ramesh
Schedulability and end-to-end latency in distributed ECU networks: formal modeling and precise estimation. EMSOFT (2010)
Deepak D'Souza, Madhu Gopinathan, S. Ramesh, Prahladavaradan Sampath
Supervisory control for real-time systems based on conflict-tolerant controllers. CASE (2009)
Aditya Kanade, Rajeev Alur, Franjo Ivancic, S. Ramesh, Sriram Sankaranarayanan, K. C. Shashidhar
Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models. CAV (2009)
Manoranjan Satpathy, Anand Yeolekar, S. Ramesh
Randomized directed testing (REDIRECT) for Simulink/Stateflow models. EMSOFT (2008)
Ambar A. Gadkari, Anand Yeolekar, J. Suresh, S. Ramesh, Swarup Mohalik, K. C. Shashidhar
AutoMOTGen: Automatic Model Oriented Test Generator for Embedded Control Systems. CAV (2008)
Rajeev Alur, Aditya Kanade, S. Ramesh, K. C. Shashidhar
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models. EMSOFT (2008)
Deepak D'Souza, Madhu Gopinathan, S. Ramesh, Prahladavaradan Sampath
Conflict-Tolerant Real-Time Features. QEST (2008)
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. DAC (2008)
Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh, K. C. Shashidhar
Behaviour Directed Testing of Auto-code Generators. SEFM (2008)
Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, S. Ramesh
Performance Analysis of FlexRay-based ECU Networks. DAC (2007)
Manoranjan Satpathy, Michael J. Butler, Michael Leuschel, S. Ramesh
Automatic Testing from Formal Specifications. TAP (2007)
Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh, K. C. Shashidhar
Testing Model-Processing Tools for Embedded Systems. IEEE Real-Time and Embedded Technology and Applications Symposium (2007)
Prahladavaradan Sampath, A. C. Rajeev, K. C. Shashidhar, S. Ramesh
How to Test Program Generators? A Case Study using flex. SEFM (2007)
Manoranjan Satpathy, S. Ramesh
Test case generation from formal models through abstraction refinement and model checking. A-MOST (2007)