Debiprasanna Sahoo

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 13

Top Topics

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Devashree Tripathy, Hadi Zamani, Debiprasanna Sahoo, Laxmi N. Bhuyan, Manoranjan Satpathy
Slumber: static-power management for GPGPU register files. ISLPED (2020)
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
Fuzzy fairness controller for NVMe SSDs. ICS (2020)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
Formal Modeling and Verification of a Victim DRAM Cache. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy
Multidimensional Grid Aware Address Prediction for GPGPU. VLSI Design (2019)
Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam
Post-Model Validation of Victim DRAM Caches. ICCD (2019)
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Srinivas Pinisetty
Formal Modeling and Verification of NAND Flash Memory Supporting Advanced Operations. ICCD (2019)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. IEEE Comput. Archit. Lett. 17 (2) (2018)
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy
DRAM cache access optimization leveraging line locking in tag cache: work-in-progress. CASES (2018)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan
CAMO: A novel cache management organization for GPGPUs. ASP-DAC (2018)
Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. VLSI Design (2017)
Debiprasanna Sahoo, Manoranjan Satpathy
MSimDRAM: Formal Model Driven Development of a DRAM Simulator. VLSI Design (2016)