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Formal Modeling and Verification of a Victim DRAM Cache.

Debiprasanna SahooSwaraj ShaManoranjan SatpathyMadhu MutyamS. RameshPartha S. Roop
Published in: ACM Trans. Design Autom. Electr. Syst. (2019)
Keyphrases
  • main memory
  • formal methods
  • memory subsystem
  • model checking
  • formal analysis
  • formal models
  • file system
  • hit rate