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Formal Modeling and Verification of a Victim DRAM Cache.
Debiprasanna Sahoo
Swaraj Sha
Manoranjan Satpathy
Madhu Mutyam
S. Ramesh
Partha S. Roop
Published in:
ACM Trans. Design Autom. Electr. Syst. (2019)
Keyphrases
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main memory
formal methods
memory subsystem
model checking
formal analysis
formal models
file system
hit rate