V. Kamakoti

ORCID

Publication Activity (10 Years)

Years Active: 1992-2023
Publications (10 Years): 18

Top Venues

J. Low Power Electron.

VLSI Design

ACM J. Emerg. Technol. Comput. Syst.

CoRR

Publications

Kaushik Raghavan, B. Sivaselavan, V. Kamakoti
iPyrDAE: Image Pyramid-Based Denoising Autoencoder for Infrared Breast Images. PReMI (2023)
Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti
Snoopy: A Webpage Fingerprinting Framework With Finite Query Model for Mass-Surveillance. IEEE Trans. Dependable Secur. Comput. 20 (5) (2023)
Sandip Saha, Sareena Karapoola, Chester Rebeiro, V. Kamakoti
YODA: Covert Communication Channel over Public DNS Resolvers. DSN (2023)
Sareena Karapoola, Nikhilesh Singh, Chester Rebeiro, V. Kamakoti
RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks. CIKM (2022)
Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti
Snoopy: A Webpage Fingerprinting Framework with Finite Query Model for Mass-Surveillance. CoRR (2022)
Prasanna Karthik Vairam, Pratyush Kumar, Chester Rebeiro, V. Kamakoti
FadingBF: A Bloom Filter With Consistent Guarantees for Online Applications. IEEE Trans. Computers 71 (1) (2022)
Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti
PERI: A Configurable Posit Enabled RISC-V Core. ACM Trans. Archit. Code Optim. 18 (3) (2021)
Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti
PERI: A Posit Enabled RISC-V Core. CoRR (2019)
Milan Patnaik, V. Kamakoti, Vashek Matyas, Vojtech Rehák
PROLEMus: A Proactive Learning-Based MAC Protocol Against PUEA and SSDF Attacks in Energy Constrained Cognitive Radio Networks. IEEE Trans. Cogn. Commun. Netw. 5 (2) (2019)
Patanjali SLPSK, Prasanna Karthik Vairam, Chester Rebeiro, V. Kamakoti
Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection. ICCAD (2019)
Patanjali SLPSK, Milan Patnaik, Seetal Potluri, V. Kamakoti
MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis. J. Low Power Electron. 14 (2) (2018)
Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, V. Kamakoti
An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. ACM J. Emerg. Technol. Comput. Syst. 14 (1) (2018)
Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti
Approximate Error Detection With Stochastic Checkers. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. DFT (2017)
N. Sathya Narayanan, Milan Patnaik, V. Kamakoti
ProMAC: A proactive model predictive control based MAC protocol for cognitive radio vehicular networks. Comput. Commun. 93 (2016)
Vikas Chauhan, Neel Gala, V. Kamakoti
ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance. VLSI Design (2016)
Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti
SHAKTI Processors: An Open-Source Hardware Initiative. VLSI Design (2016)
Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti
STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. ISLPED (2016)
Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. 11 (2) (2015)
Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. VLSI Design (2015)
Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. 12 (3) (2015)
Sukrat Gupta, Neel Gala, G. S. Madhusudan, V. Kamakoti
SHAKTI-F: A Fault Tolerant Microprocessor Architecture. ATS (2015)
Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti
DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. DATE (2015)
L. Srivani, N. H. V. Krishna Giri, Shankar Ganesh, V. Kamakoti
Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization. Appl. Soft Comput. 27 (2015)
Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. ACM Trans. Design Autom. Electr. Syst. 21 (1) (2015)
Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSI Design (2014)
Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti
-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. J. Low Power Electron. 10 (1) (2014)
K. Shyamala, V. Kamakoti
ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization. J. Low Power Electron. 10 (1) (2014)
Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. ETS (2013)
Satya Trinadh, Seetal Potluri, Ch. Sobhan Babu, V. Kamakoti
An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test. J. Low Power Electron. 9 (2) (2013)
Shri K. V. Srinivasan, V. Kamakoti, A. Bhattacharya
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays. ACM J. Emerg. Technol. Comput. Syst. 9 (1) (2013)
Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. 9 (2) (2013)
Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli
A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. J. Electr. Comput. Eng. 2012 (2012)
Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti
Interconnect Aware Test Power Reduction. J. Low Power Electron. 8 (4) (2012)
Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. 8 (5) (2012)
Shoaib Mohammed, Sk. Noor Mahammad, V. Kamakoti
Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. Appl. Soft Comput. 11 (1) (2011)
Karthik Raghavan, V. Kamakoti
ROSY: recovering processor and memory systems from hard errors. ACM SIGOPS Oper. Syst. Rev. 45 (3) (2011)
Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. ISVLSI (2011)
S. Srinivasan, V. Kamakoti, A. Bhattacharya
Towards Quick Solutions for Generalized Placement Problem. ISED (2011)
Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli
A Simulation Based Buffer Sizing Algorithm for Network on Chips. ISVLSI (2011)
Kavish Seth, V. Kamakoti, S. Srinivasan
Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. IEEE Trans. Broadcast. 56 (4) (2010)
Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti
Impact of Temperature on Test Quality. VLSI Design (2010)
Kunal Korgaonkar, K. George, M. Gautam, V. Kamakoti
HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions. ACM SIGOPS Oper. Syst. Rev. 43 (2) (2009)
George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electron. 5 (1) (2009)
K. Shyamala, J. Vimalkumar, V. Kamakoti
Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits. J. Low Power Electron. 5 (4) (2009)
Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi
Efficient Grouping of Fail Chips for Volume Yield Diagnostics. VLSI Design (2009)
Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil
Automatic Constraint Based Test Generation for Behavioral HDL Models. IEEE Trans. Very Large Scale Integr. Syst. 16 (4) (2008)
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. 4 (1) (2008)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design (2007)
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC (2007)
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. J. Low Power Electron. 3 (3) (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE (2007)
A. Pavan Kumar, V. Kamakoti, Sukhendu Das
System-on-programmable-chip implementation for on-line face recognition. Pattern Recognit. Lett. 28 (3) (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. 24 (4) (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS (2007)
Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
A novel approach to the placement and routing problems for field programmable gate arrays. Appl. Soft Comput. 7 (1) (2007)
K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
Power Virus Generation Using Behavioral Models of Circuits. VTS (2007)
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
Controllability-driven Power Virus Generation for Digital Circuits. VLSI Design (2007)
Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
FPGA based Agile Algorithm-On-Demand Co-Processor CoRR (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC (2007)
K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI (2006)
Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. VLSI Design (2006)
K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electron. 2 (3) (2006)
Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. VLSI Design (2006)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. 2 (3) (2006)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS (2005)
L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti
Pseudo-online testing methodologies for various components of field programmable gate arrays. Microprocess. Microsystems 29 (2-3) (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design (2005)
R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. VLSI Design (2005)
K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti
A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. VLSI Design (2005)
Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
FPGA based Agile Algorithm-On-Demand Co-Processor. DATE (2005)
K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil
PG) for Verification and Testing of Processor Cores. Asian Test Symposium (2005)
Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
A function generator-based reconfigurable system. ASP-DAC (2005)
Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. ASP-DAC (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA (2005)
Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. VLSI Design (2005)
A. Pavan Kumar, V. Kamakoti, Sukhendu Das
An Architecture for Real Time Face Recognition Using WMPCA. ICVGIP (2004)
Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. ICONIP (2004)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. FPT (2004)
R. Manimegalai, B. Jayaram, A. Manoj Kumar, V. Kamakoti
SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis. FPT (2004)
R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. FPL (2004)
Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. MICAI (2004)
A. Manoj Kumar, B. Jayaram, R. Manimegalai, V. Kamakoti
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays. IPDPS (2004)
Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. VLSI Design (2004)
P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam
A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design (2004)
A. Pavan Kumar, Sukhendu Das, V. Kamakoti
Face Recognition Using Weighted Modular Principle Component Analysis. ICONIP (2004)
A. Manoj Kumar, B. Jayaram, V. Kamakoti
SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. FPGA (2004)
A. Manoj Kumar, Jayaram Bobba, V. Kamakoti
MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. DATE (2004)
Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. IPDPS (2003)
L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh
On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. VLSI (2003)
L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. Asian Test Symposium (2003)
Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
An enhanced evolutionary approach to spatial partitioning for reconfigurable environments. IEEE Congress on Evolutionary Computation (2003)
B. Jayaram, A. Manoj Kumar, V. Kamakoti
Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. HiPC (2003)
M. Madhu, V. Srinivasa Murty, V. Kamakoti
Dynamic Coding Technique For Low-Power Data Bus. ISVLSI (2003)
L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
Testable Clock Routing Architecture for Field Programmable Gate Arrays. FPL (2003)
Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Ganesh, V. Kamakoti
A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. IICAI (2003)
Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
A novel three phase parallel genetic approach to routing for field programmable gate arrays. FPT (2002)
K. Srinathan, C. Pandu Rangan, V. Kamakoti
Toward Optimal Player Weights in Secure Distributed Protocols. INDOCRYPT (2001)
V. Annamalai, C. S. Krishnamoorthy, V. Kamakoti
Adaptive finite element analysis on a parallel and distributed environment. Parallel Comput. 25 (12) (1999)

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Publication Activity (10 Years)

Top Topics

Top Venues

V. Kamakoti