Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits.

K. Shyamala J. Vimalkumar V. Kamakoti

Published in: J. Low Power Electron. (2009)

Keyphrases

digital circuits
low cost
data flow
learning algorithm
cooperative
data model
dynamic programming
logic programs
power consumption
sat solvers
estimation error
model based diagnosis
finite state machines
power reduction
bounded model checking