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Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.

George KurianNarayana RaoVirendra PatidarV. KamakotiSrivaths Ravi
Published in: J. Low Power Electron. (2009)
Keyphrases
  • power reduction
  • pattern recognition
  • data streams
  • power consumption