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Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.
George Kurian
Narayana Rao
Virendra Patidar
V. Kamakoti
Srivaths Ravi
Published in:
J. Low Power Electron. (2009)
Keyphrases
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power reduction
pattern recognition
data streams
power consumption