S. Srinivasan

Publication Activity (10 Years)

Years Active: 1986-2011
Publications (10 Years): 0

Publications

S. Srinivasan, V. Kamakoti, A. Bhattacharya
Towards Quick Solutions for Generalized Placement Problem. ISED (2011)
Kavish Seth, V. Kamakoti, S. Srinivasan
Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. IEEE Trans. Broadcast. 56 (4) (2010)
Kannan Gaddam, Nitin Chandrachoodan, S. Srinivasan
Rapid Abstract Control Model for Signal Processing Implementation. SiPS (2007)
P. Rajesh Kumar, K. Sridharan, S. Srinivasan
A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment. Parallel Comput. 32 (3) (2006)
Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. VLSI Design (2006)
Seetharaman Ramachandran, S. Srinivasan
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. J. Syst. Archit. 51 (6-7) (2005)
Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. VLSI Design (2004)
Kumud Prakash Gupta, S. Srinivasan
Reduced Memory Implementation of Modified Serial Watershed Algorithm Based On Ordered Queue. ITCC (2003)
Srikar Movva, S. Srinivasan
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI. VLSI Design (2003)
A. Durga Kishore, S. Srinivasan
A Distributed Memory Architecture for Morphological Image Processing. ITCC (2003)
Seetharaman Ramachandran, S. Srinivasan
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. DSD (2003)
Seetharaman Ramachandran, S. Srinivasan
A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme. Microprocess. Microsystems 25 (9-10) (2002)
Seetharaman Ramachandran, S. Srinivasan
A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism. VLSI Design 2002 (2) (2002)
Kavish Seth, S. Srinivasan
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. VLSI Design (2002)
Seetharaman Ramachandran, S. Srinivasan
A Novel, Automatic Quality Control Scheme for Real Time Image Transmission. VLSI Design 2002 (4) (2002)
Seetharaman Ramachandran, S. Srinivasan
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. FPGA (2001)
Seetharaman Ramachandran, S. Srinivasan
A programmable pruning level control based MPEG video encoder. ISCAS (2000)
Seetharaman Ramachandran, S. Srinivasan
Design and implementation of an EPLD-based variable length coder for real time image compression applications. ISCAS (2000)
D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. VLSI Design (1999)
Seetharaman Ramachandran, S. Srinivasan, R. Chen
EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression. ISCAS (3) (1999)
P. Prabhakar Rao, S. Srinivasan
New design for an 82720-based colour graphics generator. Microprocess. Microsystems 10 (7) (1986)