Login / Signup
P. Rangarajan
Publication Activity (10 Years)
Years Active: 2004-2021
Publications (10 Years): 9
Top Topics
Machine Learning
Shortest Path
Data Retrieval
Wireless Sensor
Top Venues
Clust. Comput.
Wirel. Pers. Commun.
J. Comput. Sci.
Multim. Tools Appl.
</>
Publications
</>
S. Radhika
,
P. Rangarajan
Fuzzy Based Sleep Scheduling Algorithm with Machine Learning Techniques to Enhance Energy Efficiency in Wireless Sensor Networks.
Wirel. Pers. Commun.
118 (4) (2021)
M. S. Kavitha
,
P. Rangarajan
An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2 r Algorithm.
Circuits Syst. Signal Process.
39 (11) (2020)
N. S. Srivatchan
,
P. Rangarajan
A novel low-cost smart energy meter based on IoT for developing countries' micro grids.
Concurr. Comput. Pract. Exp.
32 (4) (2020)
D. Praveena
,
P. Rangarajan
A machine learning application for reducing the security risks in hybrid cloud networks.
Multim. Tools Appl.
79 (7-8) (2020)
S. Radhika
,
P. Rangarajan
On improving the lifespan of wireless sensor networks with fuzzy based clustering and machine learning based data reduction.
Appl. Soft Comput.
83 (2019)
K. Ilamathi
,
P. Rangarajan
Intelligent computation techniques for optimization of the shortest path in an asynchronous network-on-chip.
Clust. Comput.
22 (Suppl 1) (2019)
S. Thanga Ramya
,
Bhuvaneshwari Arunagiri
,
P. Rangarajan
Novel effective X-path particle swarm optimization based deprived video data retrieval for smart city.
Clust. Comput.
22 (6) (2019)
K. Ilamathi
,
P. Rangarajan
Determining Effective Shortest Path in Asynchronous Network-on-Chip Through Bio-Inspired Optimization Techniques.
Wirel. Pers. Commun.
102 (4) (2018)
M. S. Kavitha
,
P. Rangarajan
An optimized reconfigurable algorithm for FPGA architecture oriented IoT applications.
Cogn. Syst. Res.
52 (2018)
T. Blesslin Sheeba
,
P. Rangarajan
A Novel Substitution Box Design for humming Bird-2 against Side channel Attack.
J. Comput. Sci.
10 (9) (2014)
Kavish Seth
,
P. Rangarajan
,
S. Srinivasan
,
V. Kamakoti
,
V. Bala Kuteshwar
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation.
VLSI Design
(2004)