A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.
Vivek GargVikram ChandrasekharMilagros SashikánthV. KamakotiPublished in: ASP-DAC (2005)
Keyphrases
- learning algorithm
- segmentation algorithm
- worst case
- np hard
- significant improvement
- genetic algorithm
- hardware implementation
- detection algorithm
- search space
- preprocessing
- optimal solution
- low cost
- computational complexity
- optimization algorithm
- reduction method
- k means
- association rules
- lower bound
- probabilistic model
- matching algorithm
- convergence rate
- neural network
- fpga implementation