Milagros Sashikánth

Publication Activity (10 Years)

Years Active: 2004-2006
Publications (10 Years): 0

Publications

Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. VLSI Design (2006)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design (2005)
Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
A function generator-based reconfigurable system. ASP-DAC (2005)
Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. ASP-DAC (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA (2005)
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. FPT (2004)