V. Visvanathan

Publication Activity (10 Years)

Years Active: 1981-2015
Publications (10 Years): 1

Top Topics

Design Methodology

Top Venues

J. Low Power Electron.

Publications

Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. 11 (2) (2015)
Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSI Design (2014)
Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. 9 (2) (2013)
Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. 8 (5) (2012)
Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electron. 4 (3) (2008)
Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan
Within-die gate delay variability measurement using re-configurable ring oscillator. CICC (2008)
Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. ISQED (2005)
Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney
Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. VLSI Design (2005)
B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni
Application of Alpha Power Law Models to PLL Design Methodology. VLSI Design (2005)
Pradip Mandal, V. Visvanathan
CMOS op-amp sizing using a geometric programming formulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (1) (2001)
S. Ramanathan, S. K. Nandy, V. Visvanathan
Reconfigurable Filter Coprocessor Architecture for DSP Applications. J. VLSI Signal Process. 26 (3) (2000)
S. Ramanathan, V. Visvanathan, S. K. Nandy
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. J. VLSI Signal Process. 22 (3) (1999)
S. Ramanathan, V. Visvanathan, S. K. Nandy
Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design (1999)
Pradip Mandal, V. Visvanathan
A New Approach for CMOS Op-Amp Synthesis. VLSI Design (1999)
S. Ramanathan, V. Visvanathan, S. K. Nandy
A computational engine for multirate FIR digital filtering. Signal Process. 79 (2) (1999)
Avinash K. Gautam, V. Visvanathan, S. K. Nandy
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD (1999)
S. Ramanathan, V. Visvanathan, S. K. Nandy
Synthesis of ASIPs for DSP algorithms. Integr. 28 (1) (1999)
S. Ramanathan, V. Visvanathan
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1. Integr. 27 (1) (1999)
Pradip Mandal, V. Visvanathan
A Self-Biased High Performance Folded Cascode CMOS Op-Amp. VLSI Design (1997)
S. Ramanathan, V. Visvanathan
Low-Power Configurable Processor Array for DLMS Adaptive Filtering. VLSI Design (1997)
A. Ratan Gupta, V. Visvanathan
VLSI Implementation of DSP Architectures. VLSI Design (1996)
Pradip Mandal, V. Visvanathan
Design of high performance two stage CMOS cascode op-amps with stable biasing. VLSI Design (1996)
S. Ramanathan, V. Visvanathan
A systolic architecture for LMS adaptive filtering with minimal adaptation delay. VLSI Design (1996)
V. Visvanathan, S. Ramanathan
A modular systolic architecture for delayed least mean squares adaptive filtering. VLSI Design (1995)
Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal
High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design (1994)
V. K. Anuradha, V. Visvanathan
A CORDIC Based Programmable DXT Processor Array. VLSI Design (1994)
Pradip Mandal, V. Visvanathan
Macromodeling of the A.C. characteristics of CMOS Op-amps. ICCAD (1993)
S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan
A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP (3) (1993)
Dinesh Somasekhar, V. Visvanathan
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
S. Ramanathan, Nibedita Mohanty, V. Visvanathan
A Methodology for Generating Application Specific Tree Multipliers. VLSI Design (1993)
Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan
Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors. ICPP (3) (1993)
V. Visvanathan, Nibedita Mohanty, S. Ramanathan
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. VLSI Design (1993)
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design (1993)
Dinesh Somasekhar, V. Visvanathan
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. VLSI Design (1993)
Kalluri Eswar, P. Sadayappan, V. Visvanathan
Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors. ICPP (3) (1991)
Antony P.-C. Ng, V. Visvanathan
A Framework for Scheduling Multi-Rate Circuit Simulation. DAC (1989)
Linda S. Milor, V. Visvanathan
Detection of catastrophic faults in analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (2) (1989)
P. Sadayappan, V. Visvanathan
Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. DAC (1989)
P. Sadayappan, V. Visvanathan
Efficient sparse matrix factorization for circuit simulation on vector supercomputers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (12) (1989)
P. Sadayappan, V. Visvanathan
Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization. ICCD (1988)
P. Sadayappan, V. Visvanathan
Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor. ICS (1988)
P. Sadayappan, V. Visvanathan
Circuit Simulation on Shared-Memory Multiprocessors. IEEE Trans. Computers 37 (12) (1988)
V. Visvanathan, Linda S. Milor
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. SCG (1986)
V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
A Computational Approach for the Diagnosability of Dynamical Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 (3) (1984)
V. Visvanathan, Alberto L. Sangiovanni-Vincentelli
Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case. IEEE Trans. Computers 30 (11) (1981)
Richard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan
Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems. IEEE Trans. Computers 30 (11) (1981)