N. V. Arvind

Publication Activity (10 Years)

Years Active: 2001-2014
Publications (10 Years): 0

Top Topics

Optimal Solution

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Palkesh Jain, Frank Cano, Bapana Pudi, N. V. Arvind
Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. VLSI Design (2009)
Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. VLSI Design (2008)
Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan
Within-die gate delay variability measurement using re-configurable ring oscillator. CICC (2008)
K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu
A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. VLSI Design (2006)
Sachin Shrivastava, Dhanoop Varghese, Vikas Narang, N. V. Arvind
Improved Approach for Noise Propagation to Identify Functional Noise Violations. VLSI Design (2004)
N. V. Arvind, K. A. Rajagopal, H. S. Ajith, Das Suparna
Path Based Approach for Crosstalk Delay Analysis. VLSI Design (2004)
Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger
A Case Study of IR-Drop in Structured At-Speed Testing. ITC (2003)
Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind
Architecting ASIC libraries and flows in nanometer era. DAC (2003)
N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das
Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. VLSI Design (2001)