A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff.

K. A. Rajagopal R. Sivakumar N. V. Arvind C. Sreeram Vish Visvanathan Shailendra Dhuri Roopesh Chander Patrick Fortner Subra Sripada Qiuyang Wu

Published in: VLSI Design (2006)

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